公开(公告)号：US20190087298A1

公开(公告)日：2019-03-21

申请号：US15711028

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Anitha KONA ,  Michael John WILLIAMS ,  John Michael HORLEY ,  Alasdair GRANT

IPC: G06F11/34

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

公开(公告)号：US20230214224A1

公开(公告)日：2023-07-06

申请号：US17998299

申请日：2021-05-13

Applicant: Arm Limited

Inventor： John Michael HORLEY ,  Michael John WILLIAMS ,  Mark Salling RUTLAND ,  Alasdair GRANT

IPC: G06F9/38

CPC classification number: G06F9/3865 ,  G06F9/3867

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

公开(公告)号：US20190163601A1

公开(公告)日：2019-05-30

申请号：US16321503

申请日：2017-08-10

Applicant: ARM LIMITED

Inventor： François Christopher Jacques BOTMAN ,  Thomas Christopher GROCUTT ,  John Michael HORLEY ,  Michael John WILLIAMS

IPC: G06F11/34 ,  G06F11/36 ,  G06F9/38

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being

公开(公告)号：US20170337115A1

公开(公告)日：2017-11-23

申请号：US15532286

申请日：2015-11-23

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  John Michael HORLEY ,  Stephan DIESTELHORST

IPC: G06F11/36 ,  G06F9/46

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/455 ,  G06F9/46 ,  G06F9/467 ,  G06F11/362 ,  G06F11/3636 ,  G06F12/08 ,  G06F12/126

Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.

公开(公告)号：US20160371501A1

公开(公告)日：2016-12-22

申请号：US15189284

申请日：2016-06-22

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Michael John WILLIAMS ,  Simon John CRASKE ,  Uma Maheswari RAMALINGAM

IPC: G06F21/62

CPC classification number: G06F21/74

Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.

Abstract translation: 数据处理装置包括具有相关联的存储器存储器和一个或多个寄存器的处理元件，处理元件被配置为以两个或更多个安全模式执行处理活动，以便禁止在一个安全模式中执行的处理活动以访问 至少一些与另一个安全模式中执行的处理活动相关联的信息; 其中处理元件被配置为响应于使分支从第一安全模式中的处理活动转移到第二安全模式中的处理活动的功能调用，以将一个或多个寄存器的内容存储在存储器中 并且响应于分支返回到第一安全模式，从存储器存储器检索寄存器内容; 以及跟踪装置，被配置为生成指示所述处理元件的处理活动的跟踪数据项; 其中所述跟踪装置被配置为检测所述处理元件的分支返回操作并且生成与所述分支返回操作有关的一个或多个跟踪数据项; 并且其中所述跟踪装置被配置为响应于到所述第一安全模式的分支返回而检测所述处理元件从所述存储器存储器检索寄存器内容，并且生成与所述寄存器内容的检索相关的跟踪数据的一个或多个其它项目 从内存存储。

公开(公告)号：US20140101491A1

公开(公告)日：2014-04-10

申请号：US14104382

申请日：2013-12-12

Applicant: ARM Limited

Inventor： Paul Anthony GILKERSON ,  John Michael HORLEY ,  Michael John GIBBS

IPC: G06F11/34

CPC classification number: G06F11/3495 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30145 ,  G06F11/348

Abstract: A trace unit, diagnostic apparatus and data processing apparatus are provided for tracing of conditional instructions. The data processing apparatus generates instruction observed indicators indicating execution of conditional instructions and result output indicators indicating output by the data processing apparatus of results of executing respective conditional instructions. The instruction observed indicators and result output indicators are received by a trace unit that is configured to output conditional instruction trace data items and independently output conditional result trace data items enabling separate trace analysis of conditional instructions and corresponding conditional results by a diagnostic apparatus. The instruction observed indicator is received at the trace unit in a first processing cycle of the data processing apparatus whilst result output indicator is received at in a second different processing cycle.

Abstract translation: 提供跟踪单元，诊断装置和数据处理装置用于跟踪条件指令。 数据处理装置产生指示执行条件指令的指示观察指示，以及指示数据处理装置执行各条件指令的结果的结果输出指示符。 指令观察指标和结果输出指示器被配置为输出条件指令跟踪数据项的跟踪单元接收，并独立地输出条件结果跟踪数据项，从而能够通过诊断设备对条件指令和相应的条件结果进行单独的跟踪分析。 在数据处理装置的第一处理周期中，在跟踪单元处接收指令观察指示符，而在第二不同处理周期中接收结果输出指示符。

公开(公告)号：US20140019501A1

公开(公告)日：2014-01-16

申请号：US13934741

申请日：2013-07-03

Applicant: ARM Limited

Inventor： John Michael HORLEY ,  Andrew Brookfield Swaine ,  Michael John Williams

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/02 ,  G06F7/76 ,  G06F7/764

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

Abstract translation: 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M @ N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。

公开(公告)号：US20230385196A1

公开(公告)日：2023-11-30

申请号：US18320407

申请日：2023-05-19

Applicant: Arm Limited

Inventor： Michael John WILLIAMS ,  John Michael HORLEY

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

公开(公告)号：US20210157592A1

公开(公告)日：2021-05-27

申请号：US17096014

申请日：2020-11-12

Applicant: Arm Limited

Inventor： John Michael HORLEY ,  Simon John CRASKE

IPC: G06F9/30

Abstract: Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

公开(公告)号：US20200371891A1

公开(公告)日：2020-11-26

申请号：US16970771

申请日：2019-03-05

Applicant: Arm Limited

Inventor： John Michael HORLEY

IPC: G06F11/34 ,  G06F11/36 ,  G06F11/07 ,  G06F9/30 ,  G06F9/32

Abstract: An apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, where the sequence of instructions comprises branch instructions. Trace generating circuitry generates a trace stream of trace items indicative of the data processing operations. The trace generating circuitry is responsive to one or more not-taken branch instructions followed by a taken branch instruction in the sequence of instructions to: include at least one not-taken trace item corresponding to the one or more not-taken branch instructions followed by a taken trace item in the trace stream when a current status condition of the apparatus is met, and to include a source address associated with the taken branch instruction in the trace stream when the current status condition of the apparatus is not met. A hybrid approach between tracing not-taken branch instructions and tracing a source address associated with the taken branch instruction is thus provided.