公开(公告)号：US07405601B2

公开(公告)日：2008-07-29

申请号：US11680026

申请日：2007-02-28

申请人： Akhil K. Garlapati ,  Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

发明人： Akhil K. Garlapati ,  Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

IPC分类号： H03K21/00

CPC分类号： H03K23/66 ,  H03K21/10 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。

公开(公告)号：US07400204B2

公开(公告)日：2008-07-15

申请号：US11168012

申请日：2005-06-28

申请人： Axel Thomsen ,  Ronald G. Spencer

发明人： Axel Thomsen ,  Ronald G. Spencer

IPC分类号： H03L7/00

CPC分类号： H03L7/0895 ,  H03D13/004 ,  H03L7/1976

摘要： A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference using a phase difference to charge conversion that is substantially linear and nonzero in a phase error region that includes a phase error transition region around a phase error of zero having both negative and positive phase error values. Dual determinations, q1 and q2, offset from each other are made of an appropriate charge for a given phase error between the first and second signals. The charge pump supplies as the total charge pump output a charge value representing a combination of q1 and q2, thereby providing a phase error to charge conversion that is substantially linear in the phase error transition region around zero. A first and second output of the phase detector circuit respectively supplying UP and DOWN signals to the charge pump circuit are delayed and supplied as additional outputs of the phase detector circuit and used in generating the dual charge determinations q1 and q2.

摘要翻译： 相位检测器检测由相位检测器接收的第一和第二信号之间的相位差。 由相位差对应的电荷泵电路提供电荷，所述电荷泵电路使用在相位误差区域中基本为线性且非零的相位差的电荷转换，所述相位误差区域包括零​​相位误差为零的相位误差跃迁区域， 正相误差值。 对于第一和第二信号之间给定的相位误差，双重确定q1和q2彼此偏移由适当的电荷构成。 电荷泵作为总电荷泵输出表示q1和q2的组合的电荷值，从而在零相位误差过渡区域内提供基本为线性的电荷转换的相位误差。 分别向电荷泵电路提供UP和DOWN信号的相位检测器电路的第一和第二输出被延迟并作为相位检测器电路的附加输出提供，并用于产生双电荷确定q1和q2。

公开(公告)号：US20070075776A1

公开(公告)日：2007-04-05

申请号：US11239944

申请日：2005-09-30

申请人： Akhil Garlapati ,  Axel Thomsen

发明人： Akhil Garlapati ,  Axel Thomsen

IPC分类号： H03F3/45

CPC分类号： H03F3/45188 ,  H03F3/3061 ,  H03F3/45654 ,  H03F3/45708

摘要： A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.

摘要翻译： 互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。 负载电路可以在特定阻抗范围内具有任何阻抗。 电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。 共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。 流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

公开(公告)号：US20060119402A1

公开(公告)日：2006-06-08

申请号：US11270954

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

IPC分类号： H03B21/00

CPC分类号： H03L7/23 ,  H03L7/0898 ,  H03L7/197 ,  H03L7/1976

摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

摘要翻译： 锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器 电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。 锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比 反馈分频电路。 频率选择机构选择多个存储值中的一个。 选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

公开(公告)号：US20050242848A1

公开(公告)日：2005-11-03

申请号：US10878198

申请日：2004-06-28

申请人： Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

发明人： Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

IPC分类号： H03K23/66 ,  H03L7/00 ,  H03L7/193 ,  H03L7/197

CPC分类号： H03K23/66 ,  H03L7/193 ,  H03L7/1976

摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。

公开(公告)号：US06891430B1

公开(公告)日：2005-05-10

申请号：US09695706

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

IPC分类号： H03M3/00 ,  G06G7/12

CPC分类号： H03M3/494 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

摘要翻译： 信号处理集成电路具有斩波稳定的多级前馈放大器和ΔΣ模数转换器。 从模数转换器输出的输出的滤波包括​​一个Sinc＆lt; 5＆gt;滤波器和一个sinc＆lt; 3＆gt; 3滤波器。 可以绕过sinc <3> 3滤波器。 一个粗略的缓冲器允许在充电周期的一部分期间快速充电一个采样和保持电容器，并且在充电周期的剩余时间内可以进行更慢但更精确的充电。

公开(公告)号：US06480041B1

公开(公告)日：2002-11-12

申请号：US09695702

申请日：2000-10-25

申请人： Axel Thomsen ,  Lei Wang

发明人： Axel Thomsen ,  Lei Wang

IPC分类号： H03K500

CPC分类号： H03M3/496 ,  H03F3/005 ,  H03F3/387 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452 ,  H03M3/474

摘要： A buffer arrangement uses separate amplifiers for handling for positive going signal transitions and for negative going signal transitions respectively. A comparator detects the direction of transition and a switching element connects signal input lines in the appropriate sense to the respective amplifiers based on the output of the comparator. This permits amplifiers optimized for positive or negative going transitions to be used. The output of the amplifiers can be connected across a sampling capacitor

摘要翻译： 缓冲器配置使用单独的放大器来分别处理正向信号转换和负向信号转换。 比较器检测转换方向，并且开关元件基于比较器的输出将适当意义上的信号输入线连接到相应的放大器。 这允许使用针对正向或负向过渡进行优化的放大器。 放大器的输出可以跨采样电容连接

公开(公告)号：US6124816A

公开(公告)日：2000-09-26

申请号：US89497

申请日：1998-06-02

申请人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

发明人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

IPC分类号： H03M3/04 ,  H03M1/66

CPC分类号： H03M3/508

摘要： A digital to analog converter utilizes two discrete time processing stages, such as switched capacitor integrator circuits, operating at different sampling rates when converting the digital input signal to an analog signal. Use of two different sampling rates relaxes the requirements on antialias filters used in the continuous time processing.

摘要翻译： 数模转换器利用两个离散的时间处理级，例如开关电容积分电路，在将数字输入信号转换为模拟信号时，以不同的采样率工作。 使用两种不同的采样率可以放松对连续时间处理中使用的抗混叠滤波器的要求。

公开(公告)号：US6124815A

公开(公告)日：2000-09-26

申请号：US89495

申请日：1998-06-02

申请人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

发明人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

IPC分类号： H03M3/04 ,  H03M1/66

CPC分类号： H03M3/352 ,  H03M3/50

摘要： A integrated circuit digital to analog converter converts an M-bit digital signal to an analog output signal. The analog output signal can be used to drive external devices such as an off-chip driver. The output of the external device is sampled and fed back across the discrete time/continuous time interface on the chip to the input of the analog to digital converter. Taking the feedback point after the external device ensures relatively high performance for noise and linearity using relatively low performance components, both on and off the chip.

摘要翻译： 集成电路数模转换器将M位数字信号转换为模拟输出信号。 模拟输出信号可用于驱动外部设备，如片外驱动器。 对外部器件的输出进行采样，并将芯片上的离散时间/连续时间接口反馈到模数转换器的输入端。 在外部器件之后采取反馈点，使用相对较低性能的器件（芯片上和芯片上），确保噪声和线性度的相对较高的性能。

公开(公告)号：US6124814A

公开(公告)日：2000-09-26

申请号：US89490

申请日：1998-06-02

申请人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

发明人： Wai Laing Lee ,  Axel Thomsen ,  Lei Wang ,  Dan Kasha

IPC分类号： H03M3/04 ,  H03M1/66

CPC分类号： H03M3/368 ,  H03M3/50

摘要： A digital to analog converter converts an N-bit digital signal into an M-bit digital signal and provides the M-bit digital signal to a conversion circuit which converts the M-bit signal to an analog output signal. The analog output signal is sampled and fed back across the discrete time/continuous time interface to the input of the conversion circuit. An interpolation filter is used to increase the apparent sampling rate of the incoming N-bit signal.

摘要翻译： 数模转换器将N位数字信号转换为M位数字信号，并将M位数字信号提供给将M位信号转换为模拟输出信号的转换电路。 模拟输出信号被采样并通过离散时间/连续时间接口反馈到转换电路的输入端。 内插滤波器用于增加输入N位信号的表观采样率。