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公开(公告)号：US11921378B2
公开(公告)日：2024-03-05
申请号：US17425397
申请日：2020-10-30
Inventor： Yifu Chen , Yingying Qu , Ting Dong , Jianhua Huang , Lingdan Bo , Feng Qu
IPC: G02F1/1337 , G02F1/1343 , G02F1/1362 , G02F1/1339 , G02F1/1368
CPC classification number: G02F1/133707 , G02F1/134345 , G02F1/136286 , G02F1/13394 , G02F1/134309 , G02F1/1368
Abstract: The present disclosure relates to an electrode structure and a display panel. The electrode structure includes: first and second electrode portion and a conductive connection portion. The first electrode portion includes a first connection bar and first electrode bars. The first connection bar has a first side and a second side. The first electrode bars are located on the first side and connected to the first connection bar, and ends of adjacent first electrode bars away from the first connection bar are in an open shape. The second electrode portion includes a second connection bar and a second electrode bars. The second connection bar has a third side and a fourth side. The second electrode bars are located on the third side and connected to the second connection bar, and ends of adjacent second electrode bars away from the second connection bar are in an open shape.
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12.发明授权公开(公告)号：US11893919B2
公开(公告)日：2024-02-06
申请号：US17765373
申请日：2021-06-10
Inventor： Qiujie Su , Feng Qu , Zhihua Sun , Seungmin Lee , Yanping Liao , Hongli Yue
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G09G2310/061 , G09G2330/021
Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N−4)/2≤p≤N/2, and i is taken from 1 to (M−p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1
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公开(公告)号：US11876308B2
公开(公告)日：2024-01-16
申请号：US17630676
申请日：2021-03-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dongdong Zhang , Qianhong Wu , Shuo Zhang , Yali Wang , Zongmin Liu , Feng Qu
Abstract: The disclosure provides a micro-wave transducer and a manufacturing method thereof, and belongs to the technical field of communication. The micro-wave transducer includes: a dielectric layer having a first surface and a second surface oppositely arranged; a first electrode layer arranged on the first surface of the dielectric layer, and the reference electrode layer being provided with at least one first opening; at least one transducer electrode arranged on the second surface of the dielectric layer, wherein an orthographic projection of one transducer electrode on the dielectric layer is within an orthographic projection of one first opening on the dielectric layer; at least one first microstrip line arranged on the second surface of the dielectric layer, wherein one first microstrip line is configured to feed one transducer electrode.
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公开(公告)号：US20230401987A1
公开(公告)日：2023-12-14
申请号：US18457637
申请日：2023-08-29
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/08 , G09G2310/0286
Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1
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公开(公告)号：US11722115B2
公开(公告)日：2023-08-08
申请号：US17514895
申请日：2021-10-29
Inventor： Xiyuan Wang , Feng Qu
CPC classification number: H03H7/463 , H03H7/0115 , H03H7/175 , H03H7/1775
Abstract: The present disclosure provides a radio frequency duplexer circuit and a radio frequency substrate. The radio frequency duplexer circuit includes a first terminal, a second terminal, a third terminal, a low-pass filter, and a high-pass filter. The low-pass filter includes N first filter sub-circuits coupled in series and a first tuning sub-circuit. Among the N first filter sub-circuits coupled in series, a first end of a 1st first filter sub-circuit is coupled to the first terminal, and a second end of a Nth first filter sub-circuit is coupled to the second terminal. The high-pass filter includes M second filter sub-circuits coupled in series and a second tuning sub-circuit. Among the M second filter sub-circuits coupled in series, a first end of a 1st second filter sub-circuit is coupled to the first terminal, and a second end of a Mth second filter sub-circuit is coupled to the third terminal.
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Patent Agency Ranking
公开(公告)号：US20230006070A1
公开(公告)日：2023-01-05
申请号：US17782035
申请日：2021-05-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jie Huang , Ce Ning , Zhengliang Li , Hehe Hu , Jiayu He , Nianqi Yao , Kun Zhao , Feng Qu , Xiaochun Xu
IPC: H01L29/786 , H01L29/66 , H01L27/12
Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.
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17.发明授权公开(公告)号：US12237584B2
公开(公告)日：2025-02-25
申请号：US17780019
申请日：2021-06-23
Inventor： Xichao Fan , Zongmin Liu , Wei Li , Junwei Guo , Feng Qu , Biqi Li , Yali Wang
Abstract: Device and method controlling for an antenna, an antenna system and a computing control device are provided. The antenna includes multiple antenna array elements and multiple phase shifters for calibrating phases of the multiple antenna array elements. The device includes a temperature sensor, a positioning unit and a computing control unit, the temperature sensor is configured to obtain temperature information of the antenna and output it to the computing control unit; the positioning unit is configured to obtain position information of the antenna and output it to the computing control unit; the computing control unit is configured to receive the position information and temperature information of the antenna, determine position information of a satellite, and control the phase shifters to adjust phases of the multiple antenna array elements according to the position information the temperature information of the antenna, the position information of the satellite and pre-stored calibration data.
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18.发明申请公开(公告)号：US20250023217A1
公开(公告)日：2025-01-16
申请号：US18281111
申请日：2022-03-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Liuqing Li , Zhao Cui , Feng Qu , Qi Yao , Feng Zhang , Wenqu Liu , Liwen Dong , Zhijun Lv , Dongfei Hou , Detian Meng , Libo Wang
Abstract: A tunable phase shifter and a method for manufacturing the same, and a tunable phase shifting device. The phase shifter includes a first substrate, a second substrate, and a tunable dielectric layer between the first substrate and the second substrate; the first substrate includes a first base substrate and a first electrode on the first base substrate; the second substrate includes a second base substrate and a second electrode on the second base substrate; an orthographic projection of the first electrode on the first base substrate is at least partially overlapped with an orthographic projection of the second electrode on the first base substrate, and sheet resistances of materials of the first electrode and the second electrode are both less than or equal to 0.024Ω/□.
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公开(公告)号：US12169333B2
公开(公告)日：2024-12-17
申请号：US17921321
申请日：2021-05-12
Inventor： Jianhua Huang , Yingying Qu , Zhihua Sun , Yifu Chen , Lingdan Bo , Feng Qu , Xiaochun Xu , Shuming Wang
IPC: G02F1/1335 , G02F1/1337 , G02F1/1339
Abstract: Provided are a display panel and a display apparatus. The display panel comprises: a first substrate and a second substrate that are arranged opposite each other, wherein a display area and a frame area surrounding the display area are provided between the second substrate and the first substrate; a color resistance structure that is located in the frame area on the side of the second substrate facing the first substrate and surrounds the display area, wherein the color resistance structure comprises a first black matrix and a first color resistance portion arranged in a stacked manner; and a plurality of support bars that surround the display area, wherein each of the support bars fills a space between the color resistance structure and the first substrate.
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20.发明授权公开(公告)号：US12164733B2
公开(公告)日：2024-12-10
申请号：US17802121
申请日：2021-09-18
Abstract: The present disclosure provides a metal mesh array and a manufacturing method thereof, a thin film sensor and a manufacturing method thereof, and belongs to the field of electronic device technology. A method for manufacturing a metal mesh array includes: providing a base substrate; forming a first metal layer on the base substrate as a seed layer; forming a first interlayer dielectric layer on a side of the seed layer away from the base substrate such that the first interlayer dielectric layer includes first groove structures and second groove structures in working areas and arranged in an intersecting manner; and performing an electroplating process on the seed layer to form first metal lines in the first groove structures and second metal lines in the second groove structures. The first metal lines and second metal lines in each working area are arranged in an intersecting manner, thereby forming a metal mesh.
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