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公开(公告)号：US20180025695A1
公开(公告)日：2018-01-25
申请号：US15656419
申请日：2017-07-21
发明人： Mingfu HAN , Guangliang SHANG , Seungwoo HAN , Zhihe JIN , Xing YAO , Haoliang ZHENG , Lijun YUAN , Zhichong WANG
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2310/08 , G09G2330/08
摘要： The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.
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公开(公告)号：US20230140411A1
公开(公告)日：2023-05-04
申请号：US17905620
申请日：2021-08-12
发明人： Guangliang SHANG , Jie ZHANG , Jiangnan LU , Mei LI , Libin LIU
IPC分类号： G09G3/20
摘要： A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.
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公开(公告)号：US20230021618A1
公开(公告)日：2023-01-26
申请号：US17953941
申请日：2022-09-27
发明人： Jiangnan LU , Guangliang SHANG , Can ZHENG , Yu FENG , Libin LIU , Jie ZHANG , Mei LI
IPC分类号： H01L27/32
摘要： Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.
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14.发明申请公开(公告)号：US20220343841A1
公开(公告)日：2022-10-27
申请号：US17762330
申请日：2021-04-15
发明人： Guangliang SHANG , Libin LIU , Tian DONG , Jiangnan LU , Shiming SHI
IPC分类号： G09G3/3225 , G11C19/28
摘要： The present disclosure provides a signal generation circuit, a signal generation method, a signal generation module and a display device. The signal generating circuit includes an input terminal, a signal output terminal, a transmission control circuit, a first output circuit, and an output control circuit; the output control circuit is electrically connected to a first output control terminal, a second output control terminal, a second voltage terminal, the signal writing-in terminal, the signal output terminal and the first voltage terminal, configured to control to connect the signal writing-in terminal and the second voltage terminal under the control of a second output control signal provided by the second output control terminal, and control to connect the signal output terminal and the first voltage terminal under the control of a first output control signal provided by the first output control terminal. The present disclosure expands an adjustment range of frequency of a PWM signal.
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公开(公告)号：US20220149138A1
公开(公告)日：2022-05-12
申请号：US17427076
申请日：2020-11-13
发明人： Jiangnan LU , Guangliang SHANG , Can ZHENG , Yu FENG , Libin LIU , Jie ZHANG , Mei LI
IPC分类号： H01L27/32
摘要： An organic light-emitting diode display substrate, a display panel and a display device. The display substrate includes a source/drain layer (101), a planarization layer (102) and an anode layer (103) which are laminated in sequence; the source/drain layer (101) comprises at least one pair of first signal lines (110); the anode layer (103) comprises a common power line (130), and the common power line (130) is provided with an air discharge hole (131); and the overlapping areas of a projection pattern of the air discharge hole (131) and two first signal lines (110) in any pair of first signal lines (110) are equal, the overlapping areas are greater than 0, and the projection pattern of the air discharge hole (131) is a pattern of an orthographic projection, on the source/drain layer (101), of the air discharge hole (131) on the common power line (130). The overlapping areas of the common power line (130) and the two first signal lines (110) in the pair of first signal lines (110) are equal, so that the parasitic capacitances between the common power line (130) and the two first signal lines (110) in the pair of first signal lines (110) are the same in magnitude, and so that signals transmitted by the pair of first signal lines (110) match each other, ensuring the uniformity of a display screen.
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16.发明申请公开(公告)号：US20210358381A1
公开(公告)日：2021-11-18
申请号：US16336546
申请日：2018-08-14
发明人： Zhichong WANG , Haoliang ZHENG , Seungwoo HAN , Guangliang SHANG , Lijun YUAN , Xing YAO , Mingfu HAN
IPC分类号： G09G3/20
摘要： Disclosed is a shift register unit, including a first input circuit, an input control circuit, a pull-down control circuit, a pull-down circuit, an output circuit and a second input circuit. The first input circuit includes a first input sub-circuit, and is configured to, under control of the first signal input terminal, cause a voltage of the first voltage terminal to be output to a second terminal of the first input sub-circuit and output to the pull-up node via a first terminal thereof. The input control circuit is configured to pull down a potential of the second terminal to the potential of a first power supply voltage terminal under control of an enable signal terminal.
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公开(公告)号：US20210225312A1
公开(公告)日：2021-07-22
申请号：US16307060
申请日：2018-06-07
发明人： Mingfu HAN , Guangliang SHANG , Seung Woo HAN , Xing YAO , Haoliang ZHENG , Lijun YUAN , Zhichong WANG
摘要： A shift register unit and a drive method thereof, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a pull-up node reset circuit, an output circuit and a coupling circuit. The input circuit is configured to charge a pull-up node in response to an input signal; the pull-up node reset circuit is configured to reset the pull-up node in response to a reset signal; the output circuit is configured to output a first clock signal to a first output terminal under control of a level of the pull-up node; and the coupling circuit is configured to control, by coupling, a potential of the pull-up node in response to a second clock signal.
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公开(公告)号：US20210027699A1
公开(公告)日：2021-01-28
申请号：US16904585
申请日：2020-06-18
发明人： Haoliang ZHENG , Minghua XUAN , Dongni LIU , Ning CONG , Zhenyu ZHANG , Lijun YUAN , Yi OUYANG , Guangliang SHANG
IPC分类号： G09G3/32
摘要： Disclosed are a display panel and a display device. The display panel includes M rows and N columns of pixel units. The display panel is divided into R regions along a column direction, and an i-th region includes: (1+M(i−1)/R)-th row to a (Mi/R)-th row of pixel units. The display panel further includes M shift registers, M light emitting drivers, R light emitting control scan staring signal terminals, R scan start signal terminals for controlling time length and R scan start signal terminals for controlling current. An i-th row of pixel units is connected with an i-th shift register and an i-th light emitting driver, a light emitting driver connected to a first row of pixel units in the i-th region is connected with an i-th scan start signal terminal for controlling light emission.
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公开(公告)号：US20200258468A1
公开(公告)日：2020-08-13
申请号：US16761218
申请日：2018-11-27
发明人： Yifang CHU , Guangliang SHANG , Jieqiong WANG
摘要： A pixel compensation method, a pixel compensation device and a display device are provided. The pixel compensation method includes: determining a target sub-pixel to be compensated in a display area; setting at least one charged sub-pixel connected to a same data line as the target sub-pixel, as a reference sub-pixel; acquiring a compensation value of the target sub-pixel; and compensating a display parameter of the target sub-pixel based on the compensation value.
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公开(公告)号：US20180047343A1
公开(公告)日：2018-02-15
申请号：US15523849
申请日：2016-10-21
发明人： Feng LIAO , Guangliang SHANG , Yuting ZHANG
IPC分类号： G09G3/3283 , G05F3/26 , G09G3/3266 , H01L51/50 , G09G3/38 , G09G3/325 , G09G3/3258
CPC分类号： G09G3/3283 , G05F3/262 , G09G3/3233 , G09G3/325 , G09G3/3258 , G09G3/3266 , G09G3/38 , G09G2300/0861 , G09G2310/0251 , G09G2310/0262 , G09G2320/043 , H01L51/50
摘要： A pixel driving circuit and method, a pixel structure and display device. The pixel driving circuit includes: a driving transistor with a source electrode connected with a luminescent device; a capacitor structure with a first end connected with a gate electrode of the driving transistor; a first write control unit, configured to write a threshold voltage of the driving transistor into the first end of the capacitor structure at a write stage; a second write control unit, configured to write a data signal into a second end of the capacitor structure at the write stage; a power output control unit, configured to output a power supply signal to a drain electrode of the driving transistor at an emission stage; and a voltage follow control unit configured to control a voltage of the gate electrode to follow a change of a voltage of the source electrode of the driving transistor.
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