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11.发明授权公开(公告)号：US10304963B2
公开(公告)日：2019-05-28
申请号：US15083646
申请日：2016-03-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaoyong Lu , Dong Li , Zheng Liu , Shuai Zhang , Liang Sun , Chunping Long
IPC: H01L29/786 , H01L29/66 , H01L21/265
Abstract: The embodiments of the present disclosure provide a polysilicon thin film transistor and manufacturing method thereof, an array substrate, and a display panel. The method for manufacturing a polysilicon thin film transistor comprises: forming, on a substrate, a gate, a source and a drain, and an active layer. Forming the active layer comprises: forming a polysilicon layer on the substrate, which comprises a channel region and extension regions; performing ion injection process in the extension regions to form lightly-doped regions close to the channel region and a source region and a drain region; prior to or following the formation of the lightly-doped regions, employing halo ion injection process to form halo regions at the positions of the channel region which are close to the lightly-doped regions.
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12.发明授权公开(公告)号：US10199506B2
公开(公告)日：2019-02-05
申请号：US15084802
申请日：2016-03-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaoyong Lu , Zheng Liu , Xiaolong Li , Dong Li , Huijuan Zhang , Liang Sun
IPC: H01L29/786 , H01L29/66
Abstract: The embodiments of the present invention disclose a low temperature poly-silicon (LTPS) transistor array substrate and a method of fabricating the same, and a display device. The LTPS transistor array substrate comprises a substrate; a poly-silicon semiconductor active region provided on the substrate; a gate insulated from the poly-silicon semiconductor active region; and a dielectric spacer region provided on a side wall of the gate, wherein a portion of the poly-silicon semiconductor active region corresponding to the dielectric spacer region comprises a buffer region, and the dielectric spacer region surrounds the side wall of the gate and covers the buffer region.
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公开(公告)号：US10140911B2
公开(公告)日：2018-11-27
申请号：US15508608
申请日：2016-09-22
Inventor： Xiaoxiang Zhang , Zheng Liu , Mingxuan Liu , Huibin Guo , Xi Chen
Abstract: The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the second clock signal from the second input terminal when the pull-down control node is at the first potential level; a first pull-down circuit connected to the first pull-down node and the output terminal to control a second potential level to be passed to the output terminal when the first pull-down node is at the first potential level; a fourth node-control circuit connected to a second pull-down node and the pull-down control node to control the second pull-down node at the second potential level during the input phase and the output phase and to maintain an inverted potential level between the second pull-down node and the first pull-down node during the output-suspending phase; and a second pull-down circuit connected to the second pull-down node and the output terminal to yield a second potential level at the output terminal when the second pull-down node is at the first potential level, the first node-control circuit being further connected to the second pull-down node to control the pull-up node at the second potential level when the second pull-down node is at the first potential level.
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公开(公告)号：US10096663B2
公开(公告)日：2018-10-09
申请号：US14785777
申请日：2015-03-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zheng Liu , Xiaoyong Lu , Xiaolong Li , Chien Hung Liu , Chunping Long
Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.
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公开(公告)号：US09947697B2
公开(公告)日：2018-04-17
申请号：US14769891
申请日：2014-09-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping Long , Yinan Liang , Zheng Liu , Zuqiang Wang , Xueyan Tian
CPC classification number: H01L27/1288 , H01L27/1255 , H01L27/3262 , H01L2227/323
Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.
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Patent Agency Ranking
公开(公告)号：US09646847B2
公开(公告)日：2017-05-09
申请号：US14402872
申请日：2014-05-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zheng Liu , Jang Soon Im
IPC: H01L21/311 , H01L21/66 , H01J37/32 , H01L29/66
CPC classification number: H01L21/31116 , H01J37/32082 , H01J37/32935 , H01J37/32972 , H01J2237/334 , H01J2237/3343 , H01L22/12 , H01L22/26 , H01L29/66757 , H01L29/66765
Abstract: A method for manufacturing an array substrate, a film-etching monitoring and a film-etching monitoring device. The monitoring method comprises: monitoring and recording the transmittance reference value of a film after a film pattern is formed; and monitoring the transmittance present value of the film in real time in the process of etching an overcoating layer to form a through hole after the overcoating layer is formed on the film pattern, and monitoring the etching degree of the film by determining the variation between the transmittance present value and the transmittance reference value. The device comprises a plurality of light sources (3) and a plurality of light-sensitive probes (4) disposed in the chamber. The light sources (3) are configured to irradiate the film on a substrate; and the light-sensitive probes (4) are configured to sense the transmittance of the film.
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17.发明授权Pixel unit and method of manufacturing the same, array substrate and display device 有权像素单元及其制造方法，阵列基板和显示装置公开(公告)号：US09431434B2
公开(公告)日：2016-08-30
申请号：US14160778
申请日：2014-01-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zheng Liu , Im Jang Soon
IPC: H01L27/12 , H01L21/447 , H01L21/324
CPC classification number: H01L27/1255 , H01L27/1288
Abstract: Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are performed on a polysilicon layer so as to form heavily doped regions of a thin film transistor and a lower electrode of a storage capacitor respectively, thereby reducing numbers of photolithography and masking processes required to manufacture a LTPS-TFT, shortening time periods for development and mass production, and reducing complexity of processes as well as monitoring difficulty, and decreasing the production cost. The present invention further provides a pixel unit manufactured according to the method, an array substrate and a display device including the same.
Abstract translation: 本发明的实施例提供了一种制造像素单元的方法，其中在多晶硅层上仅执行单个图案化工艺和单个掺杂工艺，以便形成薄膜晶体管和下部电极的重掺杂区域 从而减少制造LTPS-TFT所需的光刻和掩模工艺的数量，缩短开发和批量生产的时间，并且降低工艺的复杂性以及监测难度以及降低生产成本。 本发明还提供一种根据该方法制造的像素单元，阵列基板和包括该像素单元的显示装置。
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18.发明申请公开(公告)号：US20160223901A1
公开(公告)日：2016-08-04
申请号：US14744392
申请日：2015-06-19
Inventor： Xiaoxiang Zhang , Zheng Liu , Zongjie Guo , Zhichao Zhang , Mingxuan Liu , Xi Chen
CPC classification number: G02F1/1339 , G02F1/1341 , G02F2001/133354 , G03F1/42 , G03F1/54
Abstract: An UV curing mask plate, comprising: a mask layer, wherein: the mask layer is arranged on the substrate, and has a position corresponding to alignment marks, selection marks and an area not covered by the sealing frame glue to be cured; the material of the mask layer is a material with the function of blocking UV light.
Abstract translation: 一种UV固化掩模板，包括：掩模层，其中：所述掩模层布置在所述基板上，并且具有对应于对准标记，选择标记和未被待固化的密封框胶水覆盖的区域的位置; 掩模层的材料是具有阻挡UV光的功能的材料。
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公开(公告)号：US09397125B2
公开(公告)日：2016-07-19
申请号：US14160778
申请日：2014-01-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zheng Liu , Im Jang Soon
IPC: H01L27/12 , H01L21/447 , H01L21/324
Abstract: Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are performed on a polysilicon layer so as to form heavily doped regions of a thin film transistor and a lower electrode of a storage capacitor respectively, thereby reducing numbers of photolithography and masking processes required to manufacture a LTPS-TFT, shortening time periods for development and mass production, and reducing complexity of processes as well as monitoring difficulty, and decreasing the production cost. The present invention further provides a pixel unit manufactured according to the method, an array substrate and a display device including the same.
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公开(公告)号：US20150359078A1
公开(公告)日：2015-12-10
申请号：US14500379
申请日：2014-09-29
Inventor： Zhichao Zhang , Zongjie Guo , Zheng Liu , Xiangqian Ding , Mingxuan Liu
IPC: H05F3/04
CPC classification number: H05F3/04 , H05K9/0067
Abstract: A discharge device and a display panel preparation system based thereon are disclosed. The discharge device includes a conductive contact terminal electrically connected with an electrostatic discharge contactor of a substrate to be processed; and a voltage controller electrically connected to the contact terminal for adjusting a voltage on the contact terminal. The discharge device is able to eliminate (e.g., neutralize) the static electricity on the substrate to be processed.
Abstract translation: 公开了一种基于此的放电装置和显示面板制备系统。 放电装置包括与要处理的基板的静电放电接触器电连接的导电接触端子; 电压控制器电连接到接触端子，用于调节接触端子上的电压。 放电装置能够消除（例如，中和）要处理的基板上的静电。
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