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公开(公告)号：US09831461B2
公开(公告)日：2017-11-28
申请号：US15038093
申请日：2015-11-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Young Suk Song , Seong Yeol Yoo , Seung Jin Choi , Hee Cheol Kim
CPC classification number: H01L51/5212 , C23C14/04 , C23C14/042 , H01L27/32 , H01L27/3246 , H01L51/0011 , H01L51/5228 , H01L51/56
Abstract: The present invention provides a display substrate, which includes an anode layer, a cathode layer and a luminous layer that is provided between the anode layer and the cathode layer, the anode layer including a plurality of anodes and the luminous layer including a plurality of luminous regions, wherein the display substrate further includes at least one assisting electrode, the assisting electrode being insulated and spaced from the anode, and the assisting electrode contacting with the cathode layer in parallel, such that a total resistance of the assisting electrode and the cathode layer connected in parallel is smaller than a resistance of the cathode layer alone. The IR drop in the cathode of the display substrate provided by the present invention is relatively small, such that loss of electric signals is relatively small in the cathode layer and the assisting electrode, thereby obtaining a relatively higher image quality.
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公开(公告)号：US20160005766A1
公开(公告)日：2016-01-07
申请号：US14418161
申请日：2014-04-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hyun Sic Choi , Hee Cheol Kim
IPC: H01L27/12 , H01L21/56 , H01L21/768 , H01L23/538
CPC classification number: H01L27/124 , H01L21/56 , H01L21/76877 , H01L21/76897 , H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L27/1259 , H01L2924/0002 , H01L2924/00
Abstract: The embodiments of the present invention disclose an array substrate, a method for manufacturing the same, and a display device. With the solutions of the embodiments, aperture rate is increased, and gate signal delay caused by increased connection resistance of gate line is alleviated. The array substrate of the present invention includes a thin film transistor; a substrate; a common electrode provided on the substrate; a gate line comprising a plurality of separate segments arranged to be spaced apart from each other and connected with each other through a bridge; and a common electrode line provided to be spaced apart from the gate line, the gate line and the common electrode line being in the same layer, wherein the common electrode line comprises a connection segment extending through a gap between separate segments to electrically connect with the common electrode directly.
Abstract translation: 本发明的实施例公开了阵列基板，其制造方法和显示装置。 利用实施例的解决方案，孔径率增加，并且减轻了由栅极线的连接电阻增加引起的栅极信号延迟。 本发明的阵列基板包括薄膜晶体管; 底物; 设置在基板上的公共电极; 栅极线，其包括多个分离的部分，其被布置为彼此间隔开并且通过桥彼此连接; 以及设置成与栅极线间隔开的公共电极线，栅极线和公共电极线在同一层中，其中公共电极线包括延伸穿过分离段之间的间隙的连接段，以与 公用电极直接。
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Patent Agency Ranking
公开(公告)号：US09865629B2
公开(公告)日：2018-01-09
申请号：US15122168
申请日：2015-07-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seung Jin Choi , Hee Cheol Kim , Hyun Sic Choi
IPC: H01L21/308 , H01L27/12 , H01L21/77 , H01L21/3213 , H01L21/324
CPC classification number: H01L27/1288 , H01L21/308 , H01L21/32139 , H01L21/324 , H01L21/77 , H01L27/12
Abstract: A method of manufacturing an array substrate, a display substrate and a display device are disclosed. The method of manufacturing an array substrate comprises: forming a pattern of an active layer and a pattern of source and drain electrodes on a substrate; forming a pattern of a first transparent electrode and a pattern of a passivation layer through one single patterning process; and processing the substrate on which the pattern of the passivation layer having been formed, such that a material of the passivation layer fills at least partially in a gap in the pattern of the first transparent electrode. Through forming the pattern of the first transparent electrode and the passivation layer by one single patterning process, number of masks used in the manufacturing process of the array substrate is reduced.
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公开(公告)号：US20160381814A1
公开(公告)日：2016-12-29
申请号：US15133409
申请日：2016-04-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xuefei Wang , Hee Cheol Kim
CPC classification number: H05K5/0017 , G06F1/1652 , H05K7/1401
Abstract: An embodiment of the present invention disclose a flexible display device, comprising: a housing; a supporting member, disposed inside the housing; a flexible display screen, having a first end and a second end opposite to each other, the first end being connected with the supporting member and being able to rotate around an axis; and at least one bracket rotationally connected with the housing and having a slot is arranged thereon, wherein, a side edge portion of the flexible display screen located between the first end and the second end is capable of moving along a direction of the slot under guidance of the bracket.
Abstract translation: 本发明的实施例公开了一种柔性显示装置，包括：壳体; 支撑构件，设置在所述壳体内; 柔性显示屏，其具有彼此相对的第一端和第二端，所述第一端与所述支撑构件连接并且能够绕轴线旋转; 并且至少一个托架与壳体旋转地连接并具有狭槽，其中，位于第一端和第二端之间的柔性显示屏的侧边缘部分能够在引导下沿着槽的方向移动 的支架。
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公开(公告)号：US09431432B2
公开(公告)日：2016-08-30
申请号：US14418161
申请日：2014-04-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hyun Sic Choi , Hee Cheol Kim
IPC: H01L27/12 , H01L21/56 , H01L21/768 , H01L23/538
CPC classification number: H01L27/124 , H01L21/56 , H01L21/76877 , H01L21/76897 , H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L27/1259 , H01L2924/0002 , H01L2924/00
Abstract: The embodiments of the present invention disclose an array substrate, a method for manufacturing the same, and a display device. With the solutions of the embodiments, aperture rate is increased, and gate signal delay caused by increased connection resistance of gate line is alleviated. The array substrate of the present invention includes a thin film transistor; a substrate; a common electrode provided on the substrate; a gate line comprising a plurality of separate segments arranged to be spaced apart from each other and connected with each other through a bridge; and a common electrode line provided to be spaced apart from the gate line, the gate line and the common electrode line being in the same layer, wherein the common electrode line comprises a connection segment extending through a gap between separate segments to electrically connect with the common electrode directly.
Abstract translation: 本发明的实施例公开了阵列基板，其制造方法和显示装置。 利用实施例的解决方案，孔径率增加，并且减轻了由栅极线的连接电阻增加引起的栅极信号延迟。 本发明的阵列基板包括薄膜晶体管; 底物; 设置在基板上的公共电极; 栅极线，其包括多个分离的部分，其被布置为彼此间隔开并且通过桥彼此连接; 以及设置成与栅极线间隔开的公共电极线，栅极线和公共电极线在同一层中，其中公共电极线包括延伸穿过分离段之间的间隙的连接段，以与 公用电极直接。
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公开(公告)号：US09425245B2
公开(公告)日：2016-08-23
申请号：US14101735
申请日：2013-12-10
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Young Suk Song , Seong Yeol Yoo , Seung Jin Choi , Hee Cheol Kim
CPC classification number: H01L27/3276 , H01L27/322 , H01L27/3244 , H01L51/5265 , H01L51/5271 , H01L51/56 , H01L2227/323
Abstract: Embodiments of the present invention disclose an array substrate comprising a plurality of pixel units disposed on a base substrate, the pixel units comprising: a thin film transistor structure formed on the base substrate; and an OLED driven by the thin film transistor structure, the OLED disposed in a pixel region of the pixel units, the OLED comprising sequentially in a direction away from the base substrate a first electrode which is transparent, a light-emitting layer and a second electrode which reflects light; a transflective layer disposed between the OLED and the thin film transistor structure; a color filter disposed between the second electrode of the OLED and the transflective layer; the second electrode of the OLED and the transflective layer constitute a microcavity structure.
Abstract translation: 本发明的实施例公开了一种阵列基板，包括设置在基底基板上的多个像素单元，所述像素单元包括：形成在基底基板上的薄膜晶体管结构; 以及由所述薄膜晶体管结构驱动的OLED，所述OLED设置在所述像素单元的像素区域中，所述OLED依次沿远离所述基底的方向包括透明的第一电极，发光层和第二电极 反射光的电极; 设置在OLED和薄膜晶体管结构之间的半透反射层; 设置在OLED的第二电极和半透反射层之间的滤色器; OLED的第二电极和半透反射层构成微腔结构。
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公开(公告)号：US20160064419A1
公开(公告)日：2016-03-03
申请号：US14436930
申请日：2014-08-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seung Jin Choi , Hee Cheol Kim , Young Suk Song , Seong Yeol Yoo
IPC: H01L27/12
CPC classification number: H01L27/1214 , G02F1/134309 , G02F1/1368 , H01L27/127
Abstract: The present invention discloses an array substrate, a method of manufacturing the array substrate and a display device. Since the respective surfaces of the sources, the drains and the data lines are clad by the respective insulating films, in formation of the patterns of the pixel electrodes above the insulating films by using a patterning process, the insulating films can prevent the sources and the data lines provided under them from being corroded by an etching agent when an etching process is performed to form the patterns of the pixel electrodes, so as to avoid an influence on display quality of a display panel. Furthermore, since the insulating films are formed by curing the insulating material, instead of the photoresist, remained on the patterns of the sources, the drains and the data lines when forming the patterns of the sources, the drains and the data lines by using the insulating material (replacing the photoresist), formation of the insulating films will not increase the number of masks, and a step of peeling off the insulating material is omitted. Furthermore, the respective connecting portions electrically connects the respective drains with the respective pixel electrodes through the respective first via holes A located above the respective drains and passing through the respective insulating films, so that a normal display function of the display panel can be ensured.
Abstract translation: 本发明公开了阵列基板，阵列基板的制造方法以及显示装置。 由于源极的各个表面，漏极和数据线被各自的绝缘膜包覆，所以通过使用图案化工艺形成绝缘膜上方的像素电极的图案，绝缘膜可以防止源极和源极 当进行蚀刻处理以形成像素电极的图案时，设置在其下面的数据线被蚀刻剂腐蚀，以避免对显示面板的显示质量的影响。 此外，由于通过使绝缘材料固化而形成绝缘膜，而是通过使用绝缘材料形成源的图案，排水线和数据线而不是光致抗蚀剂而残留在源的图案上，排水口和数据线 绝缘材料（替代光致抗蚀剂）时，绝缘膜的形成不会增加掩模的数量，并且省略剥离绝缘材料的步骤。 此外，各个连接部分通过位于相应的漏极上方的相应的第一通孔A将各个漏极与各个像素电极电连接并通过各个绝缘膜，从而可以确保显示面板的正常显示功能。
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