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11.发明公开公开(公告)号：US20240089003A1
公开(公告)日：2024-03-14
申请号：US17767763
申请日：2021-03-09
Inventor： Xiangye WEI , Liming XIU , Yiming BAI , Xin LI
IPC: H04B10/50
CPC classification number: H04B10/502
Abstract: An optical communication device, an optical communication system, and a method for establishing a communication connection are provided, relating to communications technology. In the optical communication device, the first driving circuit can control, based on the generated first target plaintext, the optical signal transmitting circuit to transmit the first optical signal, and control, based on the generated first key, the optical signal transmitting circuit to transmit the second optical signal. That is, an optical communication device that detects the optical signals can establish, based on the optical signals, a communication connection with the optical communication device that transmits the optical signals.
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公开(公告)号：US20240078201A1
公开(公告)日：2024-03-07
申请号：US18271865
申请日：2022-07-01
Inventor： Xiangye WEI , Liming XIU
CPC classification number: G06F13/1689 , G06F5/10 , G06F13/1621
Abstract: Provide is a FIFO memory system. The FIFO memory system includes: a FIFO memory; a read clock frequency circuit, configured to provide at least two clock signals, wherein the at least two clock signals include a first clock signal and a second clock signal, a frequency of the first clock signal being greater than a frequency of the second clock signal; and a controller, configured to determine a data volume in the FIFO memory, control the read clock frequency circuit to output the first clock signal in a case that the data volume in the FIFO memory is in a first range, or control the read clock frequency circuit to output the second clock signal in a case that the data volume in the FIFO memory is in a second range, the lower limit of the first range being not less than an upper limit of the second range.
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公开(公告)号：US20230403166A1
公开(公告)日：2023-12-14
申请号：US18033807
申请日：2020-10-28
Inventor： Xiangye WEI , Liming XIU
IPC: H04L9/32
CPC classification number: H04L9/3278 , H04L9/3236
Abstract: A data processing method, including: obtaining a challenge sequence of challenge-response pairs, and generating, by a physical unclonable function, an original response sequence corresponding to the challenge-response pairs; generating a first index parameter according to the challenge sequence, and obtaining feature bit information in the original response sequence according to the first index parameter; converting the challenge sequence to generate a second index parameter, and updating the first index parameter according to the second index parameter and the feature bit information; obtaining new feature bit information in the original response sequence according to the updated first index parameter; and repeatedly generating second index parameters, updating the first index parameter according to the second index parameters and the latest obtained feature bit information, and obtaining multiple pieces of feature bit information, to generate a target response sequence according to the multiple pieces of feature bit information.
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公开(公告)号：US20230176820A1
公开(公告)日：2023-06-08
申请号：US17778581
申请日：2021-07-07
Inventor： Xiangye WEI , Liming XIU
IPC: G06F7/58
CPC classification number: G06F7/588
Abstract: Provided is a random number generator . The random number generator includes: a control word providing circuit, a pulse generating circuit and a random number generating circuit. The control word providing circuit is configured to generate a plurality of control words in response to a first rule. The pulse generating circuit is connected to the control word providing circuit and configured to output a plurality of channels of pulse signals in response to the plurality of control words, The random number generating circuit is connected to the pulse generating circuit and configured to generate a random number sequence by performing a logical operation on the plurality of pulse signals .
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15.发明申请公开(公告)号：US20220407507A1
公开(公告)日：2022-12-22
申请号：US17765933
申请日：2021-03-09
Inventor： Xiangye WEI , Liming XIU
Abstract: A clock signal generation circuit and method, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit (10) can generate an initial clock signal having an initial frequency; a control word providing circuit (20) can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit (30) can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with the frequency control word and positively correlated with the initial frequency. It can be learned based on a relationship among the target output frequency and the initial frequency and the frequency control word that flexibly generating the frequency control word can reduce the impact of the target parameter on the frequency of the clock signal finally generated by the clock signal generation circuit.
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Patent Agency Ranking
公开(公告)号：US20220345136A1
公开(公告)日：2022-10-27
申请号：US17772482
申请日：2021-06-08
Applicant: BOE Technology Group Co., Ltd.
Inventor： Aixiang QI , Xiangye WEI , Yiming BAI , Jie FENG , Shuai WANG , Kening ZHAO
IPC: H03L7/083 , H03L7/099 , H03K3/017 , H03K19/17784
Abstract: Provided are a clock signal production circuit, a clock signal production method, and an electronic device, relating to the technical field of communications. In the clock signal production circuit, by digital circuits such as a control word generation circuit, an initial clock generation circuit, and a spread spectrum clock generation circuit, a frequency control word is first generated on the basis of spread spectrum parameters, an initial clock signal of a target duty cycle is then generated on the basis of the frequency control word, and spread spectrum processing is finally performed on the basis of the target duty cycle of the initial clock signal and the frequency control word to obtain a spread spectrum clock signal, i.e., the entire spread spectrum process is executed by the digital circuits. Therefore, it is not necessary to control the electronic device comprising the clock signal production circuit to stop working, i.e., the normal operation of the electronic device is not affected. Moreover, according to the clock signal production circuit, real-time adjustment of spread spectrum parameters (such as spread spectrum depth) that affect a spread spectrum result can be implemented, and the spread spectrum flexibility is relatively high.
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公开(公告)号：US20220131684A1
公开(公告)日：2022-04-28
申请号：US17333110
申请日：2021-05-28
Inventor： Xiangye WEI , Liming XIU
Abstract: The present disclosure provides a hash algorithm circuit, a hash algorithm method, and an electronic device. The hash algorithm circuit is used to reduce fixed-length parallel data, and the reduced identifier can be used as an index reference, an identifier ID, an address extension bit, information summary, and so on. The hash algorithm circuit has the characteristics of low power consumption, low cost, etc., and can be integrated in a digital circuit.
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公开(公告)号：US20210333931A1
公开(公告)日：2021-10-28
申请号：US16470736
申请日：2018-11-14
Inventor： Xiangye WEI
Abstract: A touch panel, a touch apparatus and a pressure touch detection method thereof. The touch panel includes: a touch electrode layer; a conductive layer, disposed opposite to the touch substrate and configured to form capacitance with the touch electrode layer; a dielectric layer, located between the touch electrode layer and the conductive layer, the dielectric layer includes a fluid dielectric layer and a solid dielectric layer, and the fluid dielectric layer has a dielectric constant larger than a dielectric constant of the solid dielectric layer, and a fluid in the fluid dielectric layer is configured to flow under the touch pressure to change the dielectric constant of the dielectric layer, so that the capacitance between the touch electrode layer and the conductive layer at the touch position and in the peripheral region of the touch position changes.
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公开(公告)号：US20210075431A1
公开(公告)日：2021-03-11
申请号：US16633287
申请日：2019-01-02
Inventor： Xiangye WEI , Liming XlU
Abstract: A frequency locked loop, an electronic device, and a frequency generation method are provided. The frequency locked loop includes: a control circuit, configured to judge a size relationship between an input frequency and a feedback frequency to obtain a control signal, and determine a frequency control word according to the control signal, in which the control signal includes a first sub-control signal and a second sub-control signal, the control circuit is configured to generate the first sub-control signal in a case where the input frequency is greater than the feedback frequency, and the control circuit is configured to generate the second sub-control signal different from the first sub-control signal in a case where the input frequency is less than the feedback frequency; and a digital control oscillation circuit, configured to generate and output an output signal having a target frequency according to the frequency control word.
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公开(公告)号：US20240184531A1
公开(公告)日：2024-06-06
申请号：US18284791
申请日：2023-01-04
Inventor： Xiangye WEI , Liming XIU
IPC: G06F7/70
CPC classification number: G06F7/70
Abstract: A stochastic computing method and circuit, a chip and a device are provided. The stochastic computing circuit includes: a control circuit, configured to input a control parameter into a pulse output circuit, the control parameter including a control word having an integer part and a decimal part; the pulse output circuit, configured to input a pulse to be computed into a computing circuit according to the control parameter, the pulse to be computed including at least one of a first sub-pulse and a second sub-pulse, and the periods of the sub-pulses being controlled by the integer part, and the probabilities that the sub-pulses appear in the pulse to be computed being controlled by the decimal part; and the computing circuit, configured to perform logic computing according to the duty cycle of the pulse to be computed and output a computing result.
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