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公开(公告)号：US06744663B2
公开(公告)日：2004-06-01
申请号：US10184811
申请日：2002-06-28
IPC分类号： G11C1115
CPC分类号： G11C11/16
摘要： A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier (1300, 1500). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier (1300, 1500). The first signal is compared to the second signal to determine the state of the MRAM cell.
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公开(公告)号：US06693824B2
公开(公告)日：2004-02-17
申请号：US10186141
申请日：2002-06-28
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.
摘要翻译： 磁阻随机存取存储器以触发方式操作，使得其写入时其逻辑状态从其当前状态翻转到备用状态。 这提供了更一致和可靠的编程，因为在切换操作期间的磁过渡能量状态是稳定的。 然而，在写入情况下，这意味着在单元被翻转之前，单元格的状态必须被读取并与单元格的期望状态进行比较。 如果单元已经处于所需的逻辑状态，则不应写入。 写入前的读取时间损失通过在读取时开始写入处理而减少，然后在单元格已经处于所需状态时中止写入步骤。 写入实际上可以在单元格上开始并被中止，而不会不利地影响单元的状态。
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公开(公告)号：US06667899B1
公开(公告)日：2003-12-23
申请号：US10401195
申请日：2003-03-27
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A magnetic memory (400) is programmed by selectively conducting current in opposite directions in both word and bit lines to reduce electromigration effects in word lines and bit lines. Various criteria, such as a data value being programmed and a previous current direction are used to determine the direction of the write currents used in the word and bit lines during programming.
摘要翻译： 通过在字线和位线中的相反方向选择性地导通电流来编程磁存储器（400），以减少字线和位线中的电迁移效应。 使用诸如正在编程的数据值和先前的当前方向的各种标准来确定在编程期间在字和位线中使用的写入电流的方向。
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公开(公告)号：US07206223B1
公开(公告)日：2007-04-17
申请号：US11297203
申请日：2005-12-07
IPC分类号： G11C11/00
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (−y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.
摘要翻译： 在写入操作期间补偿易受残余磁场影响的磁阻随机存取存储器（MRAM）（900）。 第一磁场（208）在第一时间周期内被施加到存储单元，第一磁场具有第一方向（y）和第一大小。 第二磁场（212）在第二时间段期间被施加到存储器单元并且具有第二方向（x）和第二大小。 在第三时间段期间，第三磁场（702）被施加到存储器单元，其中第三时间周期与第二时间段的至少一部分重叠，第三磁场具有近似的第三方向（-y） 与第一磁场的第一方向相反。 通过存储单元中的导体选择性地施加电流以施加三个磁场。
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公开(公告)号：US06711068B2
公开(公告)日：2004-03-23
申请号：US10184720
申请日：2002-06-28
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/062 , G11C7/067 , G11C7/14 , G11C2207/005 , G11C2207/063
摘要： A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.
摘要翻译： 存储器提供了一种感测方案，其保持数据到感测放大器的路由与参考或参考到读出放大器的路由之间的阻抗平衡。 存储器的每个子阵列具有将数据耦合到也与子阵列相邻的数据线的相邻列解码器，并且可以被认为是列解码器的一部分。 所选子阵列的数据通过其相邻数据线路由到读出放大器。 作为所选子阵列的一部分的参考被耦合到未选择的子阵列的数据线。 因此，在MRAM型存储器的情况下，参考优选地紧邻所选数据的位置，穿过相对于由数据采取的路由阻抗平衡的读出放大器的路线。
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公开(公告)号：US06711052B2
公开(公告)日：2004-03-23
申请号：US10185488
申请日：2002-06-28
IPC分类号： G11C700
CPC分类号： G11C11/16 , G11C2207/2263
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 每个具有多个串联级的可切换电流镜接收公共参考电流。 定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。 位线在公共端连接在一起，字线在公共端连接在一起。 通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。 位线组可以通过金属选项来连接，以调整编程电流的转换时间。
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17.发明授权Circuit for write field disturbance cancellation in an MRAM and method of operation 失效MRAM中的磁场干扰消除电路及其操作方法公开(公告)号：US06859388B1
公开(公告)日：2005-02-22
申请号：US10656646
申请日：2003-09-05
CPC分类号： G11C11/14
摘要： A circuit and method for counteracting stray magnetic fields generated by write currents in an MRAM memory reuses the write current in adjoining write columns via a current redistribution bus at a first end of the write lines. A first switch connected to a second end of each write line controls the write current in the write line. If the first switch is not conductive, a second switch connects the second end of the write line to a reference voltage terminal. For write lines located at sub-array edges, a predetermined amount of spacing may be used to avoid magnetic field disturbance in an adjacent sub-array. The number of spaces required can be minimized by specific activation of write line switches.
摘要翻译： 用于抵消由MRAM存储器中的写入电流产生的杂散磁场的电路和方法在写入线的第一端通过电流再分配总线重新使用相邻写入列中的写入电流。 连接到每条写入线的第二端的第一开关控制写入线中的写入电流。 如果第一开关不导通，则第二开关将写入线的第二端连接到参考电压端子。 对于位于子阵列边缘的写入线，可以使用预定量的间隔来避免相邻子阵列中的磁场干扰。 可以通过写入线开关的特定激活来最小化所需的空间数量。
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公开(公告)号：US06842365B1
公开(公告)日：2005-01-11
申请号：US10656676
申请日：2003-09-05
CPC分类号： G11C11/1695 , G11C11/1675
摘要： A write driver uses a reference current that is reflected to a driver circuit by a voltage. The driver circuit is sized in relation to the device that provides the voltage so that the current through the driver is a predetermined multiple of the reference current. This voltage is coupled to the driver circuit through a switch. The switch is controlled so that the driver circuit only receives the voltage when the write line is to have write current through it as determined by a decoder responsive to an address. The driver is affirmatively disabled when the write line is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.
摘要翻译： 写驱动器使用通过电压反映到驱动器电路的参考电流。 驱动器电路的尺寸相对于提供电压的装置的尺寸，使得通过驱动器的电流是参考电流的预定倍数。 该电压通过开关耦合到驱动电路。 开关被控制，使得驱动电路仅在响应于地址由解码器确定的写入线要具有写入电流时才接收电压。 当写行意图没有电流通过它时，驱动程序被肯定地禁用。 作为克服由于高电流引起的地面反弹的增强，驱动器的输入可以电容耦合到经历这种反弹的接地端子。 附加的增强功能可以提供幅度和边缘速率控制的优点。
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公开(公告)号：US06714440B2
公开(公告)日：2004-03-30
申请号：US10185888
申请日：2002-06-28
IPC分类号： G11C1100
CPC分类号： G11C11/15
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
摘要翻译： 磁阻随机存取存储器（MRAM）具有单独的读写路径。 每个具有多个串联级的可切换电流镜接收公共参考电流。 定时电路向字和位解码器和可切换电流镜提供控制信号，以选择性地完成通过预定写字线和预定写位线的电流路径。 位线在公共端连接在一起，字线在公共端连接在一起。 通过对连接在一起的多个写入位线的共轨进行预充电，改善了写入噪声抗扰度并使电流尖峰最小化。 位线组可以通过金属选项来连接，以调整编程电流的转换时间。
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公开(公告)号：US06538940B1
公开(公告)日：2003-03-25
申请号：US10255303
申请日：2002-09-26
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C11/16 , G11C29/12
摘要： A memory (10, 60) having at least two resistance states is tested. In one form, the memory includes a first transistor (16, 68) having a current electrode coupled to a memory cell (14, 64) and a second transistor (26, 66) having a current electrode coupled to a reference memory cell (28, 74). The control electrode of the first transistor receives either a first reference voltage or a second reference voltage based on a test control signal, and the control electrode of a second transistor receives the first reference voltage. In a test mode, after the memory cell is programmed with a resistance state, the second reference voltage (different from the first reference voltage) is provided to the first transistor. The memory cell is then read to determine whether the memory can sense the previously programmed resistance state. In one embodiment, this test mode can be used to identify weak bits in the memory.
摘要翻译： 测试具有至少两个电阻状态的存储器（10,60）。 在一种形式中，存储器包括具有耦合到存储器单元（14,64）的电流电极的第一晶体管（16,68）和具有耦合到参考存储器单元（28）的电流电极的第二晶体管（26,66） ，74）。 第一晶体管的控制电极基于测试控制信号接收第一参考电压或第二参考电压，并且第二晶体管的控制电极接收第一参考电压。 在测试模式中，在存储单元被编程为电阻状态之后，将第二参考电压（不同于第一参考电压）提供给第一晶体管。 然后读取存储器单元以确定存储器是否可以感测到先前编程的电阻状态。 在一个实施例中，该测试模式可用于识别存储器中的弱位。
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