公开(公告)号：US5798540A

公开(公告)日：1998-08-25

申请号：US848203

申请日：1997-04-29

申请人： John Bradley Boos ,  Walter Kruppa ,  Doewon Park ,  Brian R. Bennett

发明人： John Bradley Boos ,  Walter Kruppa ,  Doewon Park ,  Brian R. Bennett

IPC分类号： H01L21/308 ,  H01L21/338 ,  H01L29/201 ,  H01L29/205 ,  H01L29/778 ,  H01L29/812 ,  H01L29/00

CPC分类号： H01L29/205 ,  H01L29/201 ,  H01L29/7783

摘要： An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer. The gate air bridge fabrication is accomplished by a liquid etchant containing more than half, on volume basis, of concentrated lactic acid or acetic acid with remainder hydrogen peroxide and concentrated hydrofluoric acid. The etchant attacks InAs, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y, AlSb, and GaSb but does not attack GaAs and Au-based alloys.

摘要翻译： 一种电子器件，其特征在于具有GaAs衬底和设置在衬底上的基极，所述基底包括InAs沟道层，在沟道层上方的AlSb层，InxAl1-xAsySb1-y层至少包含位于AlSb沟道上方的In，Al和As 层InAs覆盖层设置在InAs1沟道层下方并与衬底接触的In x Al 1-x As y Sb 1-y层上方并与之接触，设置在AlSb层内的p + GaSb层，具有布置在并且接触的焊盘的肖特基栅极 与InxAl1-xAsySb1-y层，设置在InAs覆盖层上的至少一个欧姆接触，以及延伸穿过基底到衬底的沟槽，将栅极焊盘与器件隔离，并提供栅极空气桥， 门和InAs层。 门空气桥的制造是通过液体蚀刻剂来实现的，该液体蚀刻剂含有一半以上的体积基础上的浓缩乳酸或乙酸，剩余的是过氧化氢和浓缩的氢氟酸。 蚀刻剂攻击InAs，InxAl1-xAsySb1-y，AlSb和GaSb，但不会侵蚀GaAs和Au基合金。

公开(公告)号：US09006708B2

公开(公告)日：2015-04-14

申请号：US13895387

申请日：2013-05-16

申请人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

发明人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

IPC分类号： H01L29/12 ,  H01L29/205 ,  H01L29/778

CPC分类号： H01L29/122 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7785

摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.

摘要翻译： 提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。 异质结构包括InP衬底上的In0.52Al0.48As层，其中In0.52Al0.48As与InP晶格匹配，随后是In0.52Al0.48As层上的AlAsxSb1-x缓冲层，AlAsxSb1-x AlAsxSb1-x缓冲层上的间隔层，AlAsxSb1-x间隔层上的GaSb量子阱层，GaSb量子阱层上的AlAs x Sb 1-x势垒层，AlAs x Sb 1-x间隔层上的In 0.2 Al 0.8 Sb蚀刻停止层， x阻挡层和InAs帽。 半导体器件适用于诸如场效应晶体管的低功率电子器件。

公开(公告)号：US20140217363A1

公开(公告)日：2014-08-07

申请号：US13895387

申请日：2013-05-16

申请人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

发明人： Brian R. Bennett ,  Theresa F. Chick ,  Mario G. Ancona ,  John Bradley Boos

IPC分类号： H01L29/06

CPC分类号： H01L29/122 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7785

摘要： A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.

摘要翻译： 提供包括具有至少一个低电阻率p型GaSb量子阱的异质结构的半导体器件。 异质结构包括InP衬底上的In0.52Al0.48As层，其中In0.52Al0.48As与InP晶格匹配，随后是In0.52Al0.48As层上的AlAsxSb1-x缓冲层，AlAsxSb1-x AlAsxSb1-x缓冲层上的间隔层，AlAsxSb1-x间隔层上的GaSb量子阱层，GaSb量子阱层上的AlAs x Sb 1-x势垒层，AlAs x Sb 1-x间隔层上的In 0.2 Al 0.8 Sb蚀刻停止层， x阻挡层和InAs帽。 半导体器件适用于诸如场效应晶体管的低功率电子器件。

公开(公告)号：US07635879B2

公开(公告)日：2009-12-22

申请号：US11239438

申请日：2005-09-20

申请人： John Bradley Boos ,  Brian R. Bennett ,  Paul Campbell ,  Richard Magno

发明人： John Bradley Boos ,  Brian R. Bennett ,  Paul Campbell ,  Richard Magno

IPC分类号： H01L29/40

CPC分类号： H01L29/201 ,  H01L29/205 ,  H01L29/7371

摘要： This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.

摘要翻译： 本发明涉及含有半导体衬底的异质结双极晶体管，沉积在衬底上的锑基材料的缓冲层，沉积在缓冲层上的锑基材料的副集电极层，锑 - 沉积在集电极层上的锑基材料的基底层，沉积在基底层上的锑基材料的发射极层和锑基材料的覆盖层， 沉积在发射极层上。

公开(公告)号：US5426740A

公开(公告)日：1995-06-20

申请号：US181900

申请日：1994-01-14

申请人： Brian R. Bennett

发明人： Brian R. Bennett

IPC分类号： G06F13/20 ,  G06F13/36 ,  G06F13/00

CPC分类号： G06F13/20 ,  G06F13/36

摘要： An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

摘要翻译： 在多处理器系统中使用的改进的信令协议使得在I / O总线访问期间能够同时访问公共系统总线。 这减少了系统总线空闲时间，而不会将复杂性引入到系统总线架构中，否则可能会降低总线带宽增加。 改进的总线架构使用系统生成的I / O总线忙（IOBUS-BSY-）信号来向所有处理器指示I / O总线正在使用，并且所有其他I / O请求必须保持，直到当前 交易完成。 通过防止其他处理器执行I / O请求，系统总线不必保持空闲，并且可以在使用I / O总线时用于存储器到处理器和处理器到处理器事务 。 通过减少系统总线空闲的时间量，总体系统总线性能大大提高。

公开(公告)号：US4900591A

公开(公告)日：1990-02-13

申请号：US146072

申请日：1988-01-20

申请人： Brian R. Bennett ,  Joseph P. Lorenzo ,  Kenneth Vaccaro

发明人： Brian R. Bennett ,  Joseph P. Lorenzo ,  Kenneth Vaccaro

IPC分类号： C23C16/40

CPC分类号： C23C16/402

摘要： The invention comprises a pyrolytic process for the deposition of high quality silicon dioxide at temperatures of 100.degree.-330.degree. C. Deposition is achieved by reacting silane and oxygen in the 2-12 torr pressure range, yielding deposition rates of 140 .ANG./min at 300.degree. C. and 50 .ANG./min at 120.degree. C. Measurements of refractive index (1.45-1.46), field strength (3-10.times.10.sup.6 V/cm), and resistivity (10.sup.13 -10.sup.15 -cm) indicate that the oxides are near stoichiometric SiO.sub.2. This technology appears promising the Group IV and Group III-V device applications.

摘要翻译： 本发明包括用于在100-330℃的温度下沉积高质量二氧化硅的热解方法。通过在2-12乇的压力范围内使硅烷和氧气反应来实现沉积，产生140安培/分钟的沉积速率 300℃，120℃时为50安培/分钟。折射率（1.45-1.46），场强（3-10×10 6 V / cm）和电阻率（1013-1015cm）的测量表明氧化物接近 化学计量的SiO2。 该技术显示出有希望的是第IV组和第III-V组设备应用。

公开(公告)号：US20160092353A1

公开(公告)日：2016-03-31

申请号：US14496773

申请日：2014-09-25

申请人： Robert C. Swanson ,  Robert W. Cone ,  Brian R. Bennett ,  Vladimir Matveyenko ,  Paul D. Herring ,  Jordan A. Horwich ,  Tuan M. Quach ,  Cuong D. Dinh ,  Paul M. Leung ,  Luis E. Valdez ,  Joseph Hamann ,  Russell A. Hamann ,  Michael P. Pham ,  Caleb C. Molitoris ,  Kervin T. Ngo ,  Cory Li ,  Ola Fadiran ,  Jason R. Ng ,  Richard I. Guerin ,  Jay H. Danver ,  Chris Kun K. Cheung ,  Satish R. Natla ,  Rodel I. Cruz-Herrera

发明人： Robert C. Swanson ,  Robert W. Cone ,  Brian R. Bennett ,  Vladimir Matveyenko ,  Paul D. Herring ,  Jordan A. Horwich ,  Tuan M. Quach ,  Cuong D. Dinh ,  Paul M. Leung ,  Luis E. Valdez ,  Joseph Hamann ,  Russell A. Hamann ,  Michael P. Pham ,  Caleb C. Molitoris ,  Kervin T. Ngo ,  Cory Li ,  Ola Fadiran ,  Jason R. Ng ,  Richard I. Guerin ,  Jay H. Danver ,  Chris Kun K. Cheung ,  Satish R. Natla ,  Rodel I. Cruz-Herrera

IPC分类号： G06F12/06 ,  G06F12/12 ,  G06F11/30

CPC分类号： G11C29/765 ,  G06F11/3037 ,  G06F11/3055 ,  G06F12/0238 ,  G06F2201/88 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7206

摘要： Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.

摘要翻译： 系统和方法可以提供用于检测针对目标存储器区域的待决写入操作，并且确定目标存储器区域是否满足等待写入操作的退化条件。 此外，如果目标存储器区域满足劣化条件，则可以将目标存储器区域自动重新配置为冷存储区域。 在一个示例中，确定目标存储器区域是否满足劣化条件包括基于挂起的写入操作来更新针对目标存储器区域的写入操作的数量，并将写入操作的数量与偏移值进行比较，其中劣化条件是 如果写操作的数量超过偏移值，则满足。

公开(公告)号：US5900014A

公开(公告)日：1999-05-04

申请号：US769321

申请日：1996-12-19

申请人： Brian R. Bennett

发明人： Brian R. Bennett

IPC分类号： G06F11/25 ,  G06F11/34 ,  G06F11/36 ,  G06F12/08 ,  G06F11/30

CPC分类号： G06F11/3656 ,  G06F11/348 ,  G06F12/0888 ,  G06F11/25 ,  G06F2201/885

摘要： A system for facilitating debugging of software running within an information processing unit includes an external trigger state machine which selectively overrides the cacheability attribute of a cache line. An in-circuit emulator (ICE), which is used for debugging purposes, monitors addresses read by and written to a CPU. If an address which is of interest for debugging purposes is detected by the ICE, then the ICE issues a trigger signal. The trigger signal causes the external trigger state machine to designate the cache line associated with the detected address as a non-cacheable operation (i.e., to override the cacheability attribute) . Thus, the data associated with the cache line is written out to the main memory module where the data can be observed by an ICE, rather than to an internal cache memory location where the data would be invisible to an ICE. In a preferred embodiment of the invention, the external trigger state machine is configured to operate in a pipelining environment wherein multiple requests may be outstanding at one time.

摘要翻译： 用于促进在信息处理单元内运行的软件的调试的系统包括选择性地覆盖高速缓存行的高速缓存性属性的外部触发状态机。 用于调试目的的在线仿真器（ICE）监控由CPU读取和写入的地址。 如果由ICE检测到用于调试目的感兴趣的地址，则ICE发出触发信号。 触发信号使得外部触发状态机将与检测到的地址相关联的高速缓存行指定为非高速缓存操作（即，覆盖高速缓存属性）。 因此，与高速缓存线相关联的数据被写出到主存储器模块，其中可以由ICE观察数据，而不是内部高速缓冲存储器位置，其中数据将不可见于ICE。 在本发明的优选实施例中，外部触发状态机被配置为在流水线环境中操作，其中多个请求可能一次可能是未完成的。

公开(公告)号：US5404464A

公开(公告)日：1995-04-04

申请号：US16726

申请日：1993-02-11

申请人： Brian R. Bennett

发明人： Brian R. Bennett

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F12/00 ,  G06F13/14

CPC分类号： G06F12/0833 ,  G06F13/1663

摘要： An improved bus architecture system for use in a multi-processor computer system has a shared address bus and a shared data bus, and has at least two separate memory modules. The system reduces the bus latency time by allowing sequential address requests to different memory modules to begin before previous cycles are terminated. Preferably, the physical memory is mapped onto several separate memory modules which will increase the probability that concurrent address requests from different processors on the common bus are for different memory modules. The processor address determines which memory module contains the data for a new request. If the memory module addressed by the new request differs from the memory module addressed by the current request, the bus controller may issue an early address request for the new data. While the early address request for the new request is being processed, the current bus cycle for the data located in the first memory module is completed on the shared data bus. Thus, the bus latency in a tightly-coupled multi-processor system can be significantly reduced using the improved bus architecture.

摘要翻译： 用于多处理器计算机系统的改进的总线架构系统具有共享地址总线和共享数据总线，并且具有至少两个单独的存储器模块。 该系统通过在先前的周期结束之前允许对不同存储器模块的顺序地址请求开始来减少总线等待时间。 优选地，物理存储器映射到几个单独的存储器模块上，这将增加公共总线上来自不同处理器的并发地址请求对于不同存储器模块的概率。 处理器地址确定哪个内存模块包含新请求的数据。 如果由新请求寻址的存储器模块与当前请求所寻址的存储器模块不同，则总线控制器可以对新数据发出早期地址请求。 当正在处理对新请求的早期地址请求时，位于第一存储器模块中的数据的当前总线周期在共享数据总线上完成。 因此，使用改进的总线架构可以显着减少紧耦合多处理器系统中的总线延迟。

公开(公告)号：US5590299A

公开(公告)日：1996-12-31

申请号：US331290

申请日：1994-10-28

申请人： Brian R. Bennett

发明人： Brian R. Bennett

IPC分类号： G06F12/02 ,  G06F12/06 ,  G06F13/18 ,  G06F12/00

CPC分类号： G06F13/18 ,  G06F12/0607 ,  G06F12/0215

摘要： A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.

摘要翻译： 多处理器信息处理系统具有与多个CPU通信的交错存储器模块的系统总线。 多处理器系统包括监视本地CPU请求的地址的子系统监视电路。 如果本地CPU寻址与最后访问的存储器模块不同的存储器模块，则子系统监视电路启动一个请求以维持系统总线的控制。 以这种方式，通常对交错的存储器模块进行顺序写入和读取操作，使得模块恢复时间的影响被最小化。 子系统监视电路包括一个传输计数寄存器，指示在本地CPU必须放弃对系统总线的控制之前可以连续运行多少个数据传输周期。 以这种方式，对于竞争控制系统总线的其他CPU，可以确保公平的仲裁。