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    Methods of forming semiconductor devices including fin structures and related devices
    11.
    发明授权
    Methods of forming semiconductor devices including fin structures and related devices 有权
    形成包括鳍结构和相关器件的半导体器件的方法

    公开(公告)号：US07205609B2

    公开(公告)日：2007-04-17

    申请号：US10853616

    申请日：2004-05-25

    申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

    摘要： A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

    摘要翻译： 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

    Fin field effect transistors having capping insulation layers
    13.
    发明申请
    Fin field effect transistors having capping insulation layers 有权
    Fin场效应晶体管具有封盖绝缘层

    公开(公告)号：US20060202270A1

    公开(公告)日：2006-09-14

    申请号：US11433942

    申请日：2006-05-15

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

    摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

    摘要翻译： 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods
    16.
    发明授权
    Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
    异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法

    公开(公告)号：US07429504B2

    公开(公告)日：2008-09-30

    申请号：US11080737

    申请日：2005-03-15

    申请人： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    发明人： Sung-Min Kim ,  Kyoung-Hwan Yeo ,  In-Soo Jung ,  Si-Young Choi ,  Dong-Won Kim ,  Yong-Hoon Son ,  Young-Eun Lee ,  Byeong-Chan Lee ,  Jong-Wook Lee

    IPC分类号： H01L21/764 ,  H01L31/0336

    CPC分类号： H01L29/0653 ,  H01L29/78

    摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

    摘要翻译： 本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。 根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件 半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。 在本发明的实施例中可以去除第二组IV图案。 在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

    Fin field effect transistors including epitaxial fins
    17.
    发明授权
    Fin field effect transistors including epitaxial fins 有权
    Fin场效应晶体管包括外延鳍片

    公开(公告)号：US07394117B2

    公开(公告)日：2008-07-01

    申请号：US11622103

    申请日：2007-01-11

    申请人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L29/34

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Methods of fabricating fin field effect transistors
    19.
    发明授权
    Methods of fabricating fin field effect transistors 有权
    散射场效应晶体管的制造方法

    公开(公告)号：US07176067B2

    公开(公告)日：2007-02-13

    申请号：US10869763

    申请日：2004-06-16

    申请人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    发明人： In-Soo Jung ,  Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son

    IPC分类号： H01L21/339

    CPC分类号： H01L29/7851 ,  H01L21/84 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/66818 ,  H01L29/78603

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括在衬底中形成有源区，在有源区上形成外延层，去除外延层的一部分以在有源区上形成垂直鳍。 翅片具有比有源区域的宽度窄的宽度。 去除外延层的一部分可以包括氧化外延层的表面，然后去除外延层的氧化表面以减小鳍的宽度。 在去除外延层的一部分之前，外延层可以原位掺杂。 该方法还包括在鳍的顶表面和侧壁上形成导电层。 还讨论了相关晶体管。

    Methods of fabricating fin field effect transistors having capping insulation layers
    20.
    发明授权
    Methods of fabricating fin field effect transistors having capping insulation layers 有权
    制造具有封盖绝缘层的鳍式场效应晶体管的方法

    公开(公告)号：US07071048B2

    公开(公告)日：2006-07-04

    申请号：US10936033

    申请日：2004-09-08

    申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

    摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

    摘要翻译： 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。