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    Methods of forming non-volatile memory cells including fin structures
    12.
    发明授权
    Methods of forming non-volatile memory cells including fin structures 失效
    形成包括鳍结构的非易失性存储单元的方法

    公开(公告)号：US07473611B2

    公开(公告)日：2009-01-06

    申请号：US10975643

    申请日：2004-10-28

    申请人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    发明人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42316 ,  H01L29/42324 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/792

    摘要： A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

    摘要翻译： 形成非易失性存储器件的方法可以包括形成从衬底突出的翅片，在鳍的部分上形成隧道绝缘层，并且在隧道绝缘层上形成浮栅，使得隧道绝缘层在 浮动门和鳍。 可以在浮置栅极上形成电介质层，使得浮置栅极位于电介质层和鳍之间，并且可以在电介质层上形成控制栅电极，使得电介质层位于控制栅和鳍之间。 还讨论了相关设备。

    Non-volatile Memory Cells Including Fin Structures
    13.
    发明申请
    Non-volatile Memory Cells Including Fin Structures 失效
    包括鳍结构的非易失性存储单元

    公开(公告)号：US20080303079A1

    公开(公告)日：2008-12-11

    申请号：US12193200

    申请日：2008-08-18

    申请人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    发明人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42316 ,  H01L29/42324 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/792

    摘要： A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed.

    摘要翻译： 形成非易失性存储器件的方法可以包括形成从衬底突出的翅片，在鳍的部分上形成隧道绝缘层，并且在隧道绝缘层上形成浮栅，使得隧道绝缘层在 浮动门和鳍。 可以在浮置栅极上形成电介质层，使得浮置栅极位于电介质层和鳍之间，并且可以在电介质层上形成控制栅电极，使得电介质层位于控制栅和鳍之间。 还讨论了相关设备。

    Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same
    14.
    发明授权
    Nonvolatile memory cells having high control gate coupling ratios using grooved floating gates and methods of forming same 失效
    具有使用沟槽浮动栅极的高控制栅极耦合比的非易失性存储单元及其形成方法

    公开(公告)号：US07371638B2

    公开(公告)日：2008-05-13

    申请号：US11121887

    申请日：2005-05-04

    申请人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    发明人： Eun-Suk Cho ,  Choong-Ho Lee ,  Tae-Yong Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66787 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7881

    摘要： A non-volatile memory cell includes a semiconductor substrate having a fin-shaped active region extending therefrom. A tunnel dielectric layer is provided, which extends on opposing sidewalls and an upper surface of the fin-shaped active region. A floating gate electrode is provided on the tunnel dielectric layer. This floating gate electrode has at least a partial groove therein. An inter-gate dielectric layer is also provided. This inter-gate dielectric layer extends on the floating gate electrode and into the at least a partial groove. A control gate electrode is provided, which extends on the inter-gate dielectric layer and into the at least a partial groove.

    摘要翻译： 非易失性存储单元包括具有从其延伸的鳍状有源区的半导体衬底。 提供隧道电介质层，其在相对的侧壁上延伸并且在鳍状有源区域的上表面上延伸。 在隧道电介质层上设置浮栅电极。 该浮栅电极中至少有一部分凹槽。 还提供了栅极间电介质层。 该栅极间电介质层在浮栅电极上延伸并进入至少一部分槽。 提供控制栅极电极，其在栅极间电介质层上延伸并且进入至少部分凹槽。

    Method for forming a FinFET by a damascene process
    15.
    发明授权
    Method for forming a FinFET by a damascene process 有权
    通过镶嵌工艺形成FinFET的方法

    公开(公告)号：US07358142B2

    公开(公告)日：2008-04-15

    申请号：US11046623

    申请日：2005-01-28

    申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

    摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源区和漏区形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

    Method of fabricating a semiconductor device having self-aligned floating gate and related device
    16.
    发明授权
    Method of fabricating a semiconductor device having self-aligned floating gate and related device 有权
    制造具有自对准浮动栅极和相关器件的半导体器件的方法

    公开(公告)号：US07329580B2

    公开(公告)日：2008-02-12

    申请号：US11425205

    申请日：2006-06-20

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Tae-Yong Kim ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Tae-Yong Kim ,  Dong-Gun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7851

    摘要： A semiconductor device such as a flash memory device having a self-aligned floating gate and a method of fabricating the same is provided. An embodiment of the device includes an isolation layer defining a fin body is formed in a semiconductor substrate. The fin body has a portion protruding above the isolation layer. A sacrificial pattern is formed on the isolation layer. The sacrificial pattern has an opening self-aligned with the protruding portion of the fin body. The protruding fin body is exposed in the opening. An insulated floating gate pattern is formed to fill the opening. The sacrificial pattern is then removed. An inter-gate dielectric layer covering the floating gate pattern is formed. A control gate conductive layer is formed over the inter-gate dielectric layer. The control gate conductive layer, the inter-gate dielectric layer, and the floating gate pattern are patterned to form a control gate electrode crossing the fin body as well as the insulated floating gate interposed between the control gate electrode and the fin body.

    摘要翻译： 提供了诸如具有自对准浮动栅极的闪速存储器件及其制造方法的半导体器件。 该器件的一个实施例包括在半导体衬底中形成限定翅片体的隔离层。 翅片本体具有突出在隔离层上方的部分。 在隔离层上形成牺牲图案。 牺牲图案具有与翅片体的突出部分自对准的开口。 突出的翅片体露出开口。 形成绝缘浮栅图形以填充开口。 然后去除牺牲图案。 形成覆盖浮栅图案的栅极间介电层。 在栅极间电介质层上形成控制栅极导电层。 对控制栅极导电层，栅极间电介质层和浮置栅极图案进行图案化以形成跨越鳍体的控制栅电极以及插在控制栅电极和鳍体之间的绝缘浮栅。

    Non-volatile memory device and method of manufacturing the same
    17.
    发明授权
    Non-volatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07259430B2

    公开(公告)日：2007-08-21

    申请号：US11073134

    申请日：2005-03-04

    申请人： Jae-Man Yoon ,  Tae-Yong Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    发明人： Jae-Man Yoon ,  Tae-Yong Kim ,  Dong-Gun Park ,  Choong-Ho Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7851

    摘要： A non-volatile memory device includes a fin body protruded from a semiconductor substrate. The fin body has first and second side surfaces opposite to each other. An inner dielectric layer pattern is formed on an upper surface, and the first and second side surfaces of the fin body. A floating gate electrode is formed on the inner dielectric layer pattern. The floating gate electrode has an uneven upper surface. An outer dielectric layer is formed on the floating gate electrode. A control gate electrode is formed on the outer dielectric layer.

    摘要翻译： 非易失性存储器件包括从半导体衬底突出的翅片体。 翅片体具有彼此相对的第一和第二侧表面。 在上表面以及翅片体的第一和第二侧表面上形成内部电介质层图案。 在内部电介质层图案上形成浮栅电极。 浮栅电极具有不均匀的上表面。 外电介质层形成在浮栅电极上。 控制栅电极形成在外电介质层上。

    Method for forming a FinFET by a damascene process
    18.
    发明申请
    Method for forming a FinFET by a damascene process 有权
    通过镶嵌工艺形成FinFET的方法

    公开(公告)号：US20050170593A1

    公开(公告)日：2005-08-04

    申请号：US11046623

    申请日：2005-01-28

    申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8228 ,  H01L29/786 ,  H01M8/00

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

    摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源极和漏极区域形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

    Battery module including a relay installed to a case
    20.
    发明授权
    Battery module including a relay installed to a case 有权
    电池模块包括安装在外壳上的继电器

    公开(公告)号：US09093851B2

    公开(公告)日：2015-07-28

    申请号：US13402828

    申请日：2012-02-22

    申请人： Shi-Dong Park ,  Tae-Yong Kim

    发明人： Shi-Dong Park ,  Tae-Yong Kim

    IPC分类号： H02J7/00 ,  B60L3/00 ,  B60L3/04 ,  B60L11/18

    CPC分类号： H02J7/0045 ,  B60L3/0046 ,  B60L3/04 ,  B60L11/1879 ,  B60L2240/545 ,  B60L2240/547 ,  B60L2240/549 ,  Y02T10/7005

    摘要： A battery module including: a battery assembly including a plurality of rechargeable batteries; a case receiving the battery assembly; a battery management system (BMS) managing unit batteries of the battery assembly; and a relay installed to the case on an output line of the battery assembly and including a relay body configured to selectively block a current according to a signal of the BMS; a connection bar connected to the relay body; and an output terminal connected to the relay body via the connection bar and fastened to the case at a location spaced apart from the relay body.

    摘要翻译： 一种电池模块，包括：电池组件，其包括多个可充电电池; 接收电池组件的壳体; 管理电池组的电池管理系统（BMS）; 以及继电器，其安装在所述电池组件的输出线上的壳体上，并且包括被配置为根据所述BMS的信号选择性地阻挡电流的中继体; 连接到所述继电器主体的连接杆; 以及输出端子，经由所述连接杆连接到所述继电器主体，并且在与所述继电器主体间隔开的位置处紧固到所述壳体。