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公开(公告)号：US12026093B1
公开(公告)日：2024-07-02
申请号：US17883249
申请日：2022-08-08
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/08 , G06F12/0802 , G06F12/1009
CPC classification number: G06F12/0802 , G06F12/1009 , G06F2212/60
Abstract: A data storage system has a CPU data bus for reading and writing data to data accelerators. Each data accelerator has a controller which receives the read and write requests and determines whether to read or write a local cache memory in preprocessed form or an attached accelerator memory which has greater size capacity based on entries in an address translation table (ATT) and saves data in a raw unprocessed form. The controller may also include an address translation table for mapping input addresses to memory addresses and indicating the presence of data in preprocessed form.
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公开(公告)号：US11921843B2
公开(公告)日：2024-03-05
申请号：US17485471
申请日：2021-09-26
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Heonchul Park , Venkat Mattela
CPC classification number: G06F21/52 , G06F9/3804 , G06F11/1629 , G06F2221/033
Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.
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公开(公告)号：US11775306B2
公开(公告)日：2023-10-03
申请号：US17677198
申请日：2022-02-22
Applicant: Ceremorphic, Inc.
CPC classification number: G06F9/3836 , G06F9/30123 , G06F9/30145 , G06F9/3802 , G06F9/3851 , G06F9/52
Abstract: A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.
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公开(公告)号：US11700001B1
公开(公告)日：2023-07-11
申请号：US17589845
申请日：2022-01-31
Applicant: Ceremorphic, Inc.
Inventor： Sanghamitra Debroy , Akshaykumar Salimath , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. A first substrate, a second substrate and a third substrate is provided. A first input nanomagnet is disposed over the first substrate, a second input nanomagnet is disposed over the second substrate, and a third input nanomagnet is disposed over the third substrate. A spacer layer is disposed over the first input nanomagnet, the second input nanomagnet, and the third input nanomagnet. An output magnet is disposed over the spacer layer.
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公开(公告)号：US11632324B2
公开(公告)日：2023-04-18
申请号：US17334704
申请日：2021-05-29
Applicant: Ceremorphic, Inc.
Inventor： Robert Wiser , Venkat Mattela , Wei Xiong
IPC: H04L45/02
Abstract: A node mesh contains an originating node coupled to one or more nodes, each node having an communications interface input and a communications interface output. Each node has a route table with an association between a header amplitude and an output interface, such that a header having a particular amplitude causes the input node which received the message to couple the message to an associated communications interface output of the node. When the originating node outputs a message with a header amplitude, each node of the node mesh in turn directs the message to an output interface as directed by the node local route table to a terminating node of the node mesh, where the terminating node may be a training processor or inference processor for machine learning applications.
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Patent Agency Ranking
公开(公告)号：US12300411B1
公开(公告)日：2025-05-13
申请号：US17978160
申请日：2022-10-31
Applicant: Ceremorphic, Inc.
Inventor： Sanghamitra Debroy , Akshaykumar Salimath , Venkat Mattela
Abstract: A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.
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公开(公告)号：US12218668B1
公开(公告)日：2025-02-04
申请号：US18115727
申请日：2023-02-28
Applicant: Ceremorphic, Inc.
Inventor： Akshaykumar Salimath , Sanghamitra Debroy , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. A substrate is provided. Three nanotracks are disposed over the substrate and intersect in a central portion. Two nanotracks are disposed about a first axis and one nanotrack is disposed about a second axis perpendicular to the first axis. A ground pad is disposed in the central portion. An input value is set by nucleating a skyrmion about a first end of the nanotracks disposed about the first axis. Presence of the skyrmion indicates a first value and absence indicates a second value. A charge current is passed in the substrate, along the first axis to move the nucleated skyrmions towards the central portion. Presence of the skyrmion is sensed in the central portion and indicates a first value when skyrmion is present.
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公开(公告)号：US12218667B1
公开(公告)日：2025-02-04
申请号：US18104208
申请日：2023-01-31
Applicant: Ceremorphic, Inc.
Inventor： Akshaykumar Salimath , Sanghamitra Debroy , Venkat Mattela
Abstract: A system and method for a logic device is disclosed. Three synthetic antiferromagnet (SAF) nanotracks are disposed over a substrate along a first axis. A connector nanotrack connects the three input nanotrack about a second end of the nanotracks. An output nanotrack is disposed about a central portion of the connector nanotrack. An input value is defined at a first end of the input nanotracks by selectively nucleating a SAF skyrmion at the first end. Presence of the skyrmion is indicative of a first value and absence of the skyrmion indictive of a second value. A charge current is passed along the first axis to selectively move nucleated skyrmion to the output nanotrack, with presence of Skyrmion indicating an output value of the first value.
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公开(公告)号：US12105625B2
公开(公告)日：2024-10-01
申请号：US17588240
申请日：2022-01-29
Applicant: Ceremorphic, Inc.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/04 , G06N3/0464 , G06N3/10
CPC classification number: G06F12/04 , G06N3/0464 , G06N3/10 , G06F2212/16
Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
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公开(公告)号：US12072799B2
公开(公告)日：2024-08-27
申请号：US18121294
申请日：2023-03-14
Applicant: CEREMORPHIC, INC.
Inventor： Lizy Kurian John , Venkat Mattela , Heonchul Park
IPC: G06F12/04 , G06N3/0464 , G06N3/10
CPC classification number: G06F12/04 , G06N3/0464 , G06N3/10 , G06F2212/16
Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.
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