公开(公告)号：US10255403B1

公开(公告)日：2019-04-09

申请号：US14988808

申请日：2016-01-06

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sneh Saurabh ,  Naresh Kumar

IPC: G06F17/50

Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

公开(公告)号：US09727676B1

公开(公告)日：2017-08-08

申请号：US15072162

申请日：2016-03-16

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sneh Saurabh ,  Naresh Kumar

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031

Abstract: For a circuit path to be represented in a timing model, a set of propagating waveforms substantially converges through waveform stabilization to a uniform waveform at a waveform invariant node and all pins following. The circuit path is decomposed at the waveform invariant node into first and second portions, which are characterized as first and second timing arcs. In computing output slew and delay values, the first timing arc generation factors only a single output load of the waveform invariant node, and the second timing arc generation factors only the uniform waveform. Similarly, a setup arc employs the uniform waveform rather than multiple clock input waveforms in computing setup/hold values. Simulation of waveform propagation is also simplified by simulating only the uniform waveform for the second portion. Additionally, the first arc may be shared between a plurality of circuit paths which share an input pin and the waveform invariant node.

公开(公告)号：US11531803B1

公开(公告)日：2022-12-20

申请号：US17232616

申请日：2021-04-16

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Marut Agarwal ,  Rakesh Agarwal

IPC: G06F30/398 ,  G06F119/12

Abstract: A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

公开(公告)号：US09589096B1

公开(公告)日：2017-03-07

申请号：US14716059

申请日：2015-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Vishnu Kumar ,  Manish Bansal ,  Naresh Kumar ,  Manuj Verma ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract translation: 方法和系统提供SPICE结果的设置和生成，用于一组定时路径以及SPICE仿真与静态时序分析（STA）基于路径的结果生成的集成。 在一个实施例中，方法可以选择候选的定时路径集合，在所选择的路径上执行基于路径的分析（PBA），为所选择的路径生成SPICE结果，并将PBA和SPICE结果呈现在集成的用户界面中以便于签名 基于注释约束和STA结果与SPICE结果之间的相关性。 本公开的方法和系统尤其涉及在电子设计和验证过程中的定时签发。

公开(公告)号：US09529962B1

公开(公告)日：2016-12-27

申请号：US14732160

申请日：2015-06-05

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Pradeep Yadav ,  Manuj Verma ,  Naresh Kumar ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: The present disclosure relates to a computer-implemented method for use with an electronic design. Embodiments include identifying, using one or more processors, a plurality of sibling nets associated with the electronic design and determining if the plurality of sibling nets have a same input slew rate. If the plurality of sibling nets do not have a same input slew rate, embodiments also include determining a delay calculation (DC) for each of the plurality of sibling nets. If the plurality of sibling nets do have a same input slew rate, embodiments further include sharing a stored DC with the plurality of sibling nets.

Abstract translation: 本公开涉及一种用于电子设计的计算机实现的方法。 实施例包括使用一个或多个处理器识别与电子设计相关联的多个兄弟网，并确定多个兄弟网是否具有相同的输入转换速率。 如果多个兄弟网不具有相同的输入压摆率，则实施例还包括确定多个兄弟网中的每一个的延迟计算（DC）。 如果多个兄弟网确实具有相同的输入转换速率，则实施例还包括与多个兄弟网共享存储的DC。

公开(公告)号：US08938703B1

公开(公告)日：2015-01-20

申请号：US14338272

申请日：2014-07-22

Applicant: Cadence Design Systems, Inc.

Inventor： Sneh Saurabh ,  Naresh Kumar ,  Igor Keller

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F2217/84

Abstract: Systems and methods for generating Extracted Timing Models (ETM) for use in an analysis of the timing of an integrated circuit design in which common paths that contribute to Common Path Pessimism (CPP) are identified and included in the generated ETM such that a CPP removal algorithm implemented during the timing analysis will be properly adjusted to remove such pessimism. To generate an ETM, the clock latency paths will be characterized, taking into account the pins and timing arcs that are necessary for the identification and removal of common path pessimism, the timing information of the topologically crucial points of the design block will be retained in the ETM, and the non-essential and noisy information will be removed from the ETM to ensure that the ETM is robust and compact.

Abstract translation: 用于生成提取时序模型（ETM）的系统和方法用于分析集成电路设计的时序，其中有助于通用路径悲观（CPP）的共同路径被识别并包含在生成的ETM中，使得CPP去除 在时序分析过程中实现的算法将被适当调整，以消除这种悲观情绪。 为了生成ETM，时钟延迟路径将被特征化，考虑到识别和消除公共路径悲观情况所需的引脚和定时弧，设计块的拓扑关键点的定时信息将保留在 ETM和非必要和嘈杂的信息将从ETM中删除，以确保ETM稳健且紧凑。

公开(公告)号：US11514218B1

公开(公告)日：2022-11-29

申请号：US17390247

申请日：2021-07-30

Applicant: Cadence Design Systems, Inc.

Inventor： Hemendra Singh Negi ,  Naresh Kumar ,  Arunjai Singh

IPC: G06F30/3315 ,  G06F30/31 ,  G06F119/12 ,  G06F111/02

Abstract: Embodiments include herein are directed towards a method for static timing analysis. Embodiments included herein may include providing, using at least one processor, a database of predefined script tags and causing a display of a script at a graphical user interface. Embodiments may also include receiving an insertion of at least one tag from the database within the script and generating one or more timing reports based upon, at least in part, the script and the at least one tag.