公开(公告)号：US5146307A

公开(公告)日：1992-09-08

申请号：US700746

申请日：1991-05-15

申请人： Cetin Kaya

发明人： Cetin Kaya

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/525

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L21/31662 ,  H01L21/76888 ,  H01L23/5222 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A method for forming a fuse for integrated circuits and a fuse produced therefrom is disclosed. The fuse (10) includes a substrate (12) having thick oxide layers (14) with a gap (16) formed therebetween. A second oxide layer (20) is grown onto an N+ region (18). At the intersection between oxide layers (20, 14), a sublithographic area is exposed and a dielectric layer (24) is formed therein. This structure is capable of reducing the capacitance between a polysilicon layer (26) formed thereon and the N+ diffusion region (18).

摘要翻译： 公开了一种用于形成用于集成电路的熔丝的方法和由其产生的保险丝。 保险丝（10）包括具有厚氧化物层（14）的衬底（12），其间形成有间隙（16）。 第二氧化物层（20）生长在N +区域（18）上。 在氧化物层（20,14）的交点处，露出亚光刻区域，并在其中形成电介质层（24）。 该结构能够减小其上形成的多晶硅层（26）和N +扩散区域（18）之间的电容。

公开(公告)号：US5130267A

公开(公告)日：1992-07-14

申请号：US784097

申请日：1991-10-28

申请人： Cetin Kaya ,  Howard L. Tigelaar

发明人： Cetin Kaya ,  Howard L. Tigelaar

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/822 ,  H01L29/423

CPC分类号： H01L28/40 ,  H01L21/28273 ,  H01L29/4232 ,  H01L29/66825

摘要： A metal-to-polysilicon capacitor, a floating-gate transistor containing such a capacitor, and a method for making the same is disclosed. The bottom plate of the capacitor is formed over a field oxide structure, and the capacitor dielectric is deposited thereover. A first metal layer, such as titanium nitride or a titanium-tungsten alloy, is formed over the capacitor dielectric, and is patterned and etched to define the top plate of the capacitor and, accordingly, the capacitor size. Multilevel dielectric is formed thereover, and a contact via to the top plate is etched therethrough. Metallization is sputtered overall, to make contact to the top plate and elsewhere in the circuit.

摘要翻译： 公开了一种金属到多晶硅电容器，含有这种电容器的浮栅晶体管及其制造方法。 电容器的底板形成在场氧化物结构上，并且电容器电介质沉积在其上。 在电容器电介质上形成第一金属层，例如氮化钛或钛 - 钨合金，并对其进行图案化和蚀刻以限定电容器的顶板，并因此限定电容器尺寸。 在其上形成多层电介质，并且通过其到达顶板的接触通孔被蚀刻。 金属化整体溅出，以接触顶板和电路中的其他地方。

公开(公告)号：US07795970B2

公开(公告)日：2010-09-14

申请号：US12369489

申请日：2009-02-11

申请人： Cetin Kaya ,  Adam Shook

发明人： Cetin Kaya ,  Adam Shook

IPC分类号： H03F3/217

CPC分类号： H03F3/217

摘要： Pulse-width-modulating class D amplifier with an H-bridge output stage, and method of operating the same. in which output stage dead-time is compensated. Offset logic circuitry detects various dead-time-related conditions at push-pull output drivers, and generates an offset signal applied to the amplified differential input signal, to adjust the time at which the voltage at differential signal lines crosses a ramp reference waveform. The offset signal can correspond to the duration of a disturbance (dead-time at one driver in combination with an active signal at the active driver), or the sum of that disturbance duration with a dead-time at the active driver. The offset signal is generated by charging a capacitor for the duration of this disturbance, or disturbance plus dead-time. According to another approach, error is reduced by charging a capacitor for each transition of the signal for a duration of the dead-time of the active driver. Total harmonic distortion is reduced without requiring increased circuit complexity and without shortening the dead-time to unsafe margins.

摘要翻译： 具有H桥输出级的脉宽调制D类放大器及其操作方法。 其中输出级死区时间被补偿。 偏移逻辑电路检测推挽输出驱动器处的各种死区时间相关条件，并产生施加到放大的差分输入信号的偏移信号，以调整差分信号线上的电压与斜坡参考波形相交的时间。 偏移信号可以对应于扰动的持续时间（一个驱动器的死区时间与有源驱动器上的有效信号的组合），或者该有效驱动器的干扰持续时间与死区时间的总和。 偏移信号是通过在这种干扰持续时间内对电容充电或扰动加上死区而产生的。 根据另一种方法，通过在有源驱动器的死区时间的持续时间内对信号的每个转换充电电容来减少误差。 减少总谐波失真，而不需要增加电路复杂性，并且不会缩短到不安全边缘的死区时间。

公开(公告)号：US07626793B2

公开(公告)日：2009-12-01

申请号：US11339786

申请日：2006-01-25

申请人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

发明人： Cetin Kaya ,  James Teng ,  Claus Neesgaard

IPC分类号： H02H3/08 ,  H02H9/02 ,  H02H3/00

CPC分类号： H03K17/082

摘要： A circuit and method for determining overcurrent in a FET detects an output voltage of the FET in both a positive and negative polarity. The related positive or negative currents through the FET can be measured to determine whether an overcurrent condition exists. By measuring positive and negative currents in the FET, the overcurrent detector can obtain twice as much information as when measuring a positive current alone, and can respond more readily to overcurrent conditions. The overcurrent detector avoids the constraints typically observed in cycle-by-cycle PWM control with single polarity Vds sensing, while permitting a relaxation in the timing requirements for current sensing. A spike suppression circuit also contributes to longer sensing intervals.

摘要翻译： 用于确定FET中的过电流的电路和方法以正负极性检测FET的输出电压。 可以测量通过FET的相关正或负电流以确定是否存在过电流状况。 通过测量FET中的正电流和负电流，过电流检测器可以获得与单独测量正电流时相同的信息量的两倍，并且可以更容易地响应过电流条件。 过电流检测器避免了在单极性Vds感测的逐周期PWM控制中通常观察到的约束，同时允许电流感测的定时要求松弛。 尖峰抑制电路还有助于更长的感测间隔。

公开(公告)号：US07342447B2

公开(公告)日：2008-03-11

申请号：US11124885

申请日：2005-05-09

申请人： Shifeng Zhao ,  Cetin Kaya ,  Sreenath Unnikrishnan

发明人： Shifeng Zhao ,  Cetin Kaya ,  Sreenath Unnikrishnan

IPC分类号： H03F3/217

CPC分类号： H03F3/45183 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/217 ,  H03F3/3033 ,  H03F3/45188 ,  H03F3/72 ,  H03F2200/462 ,  H03F2200/471

摘要： A system and method is provided for driving an output transistor. The system and method employ a sense control to adjust a drive strength associated with driving the output transistor. The sense control measures an output parameter of the transistor, and adjusts the drive strength based on the measured parameter. The drive strength can be based on a selected driver of a plurality of driver devices with varying drive strengths or selected output devices of a driver of a plurality of output devices of varying drive strengths. The drive strength of the driver devices or output devices can be varied by varying the channel widths of output drive devices selectively coupled to a drive terminal (e.g., gate, base) of the output transistor.

摘要翻译： 提供了用于驱动输出晶体管的系统和方法。 该系统和方法采用感测控制来调节与驱动输出晶体管相关联的驱动强度。 感测控制测量晶体管的输出参数，并根据测量参数调整驱动强度。 驱动强度可以基于具有变化驱动强度的多个驱动器装置的选定驱动器或具有变化驱动强度的多个输出装置的驱动器的选定输出装置。 可以通过改变选择性地耦合到输出晶体管的驱动端子（例如，栅极，基极）的输出驱动器件的沟道宽度来改变驱动器器件或输出器件的驱动强度。

公开(公告)号：US07304344B1

公开(公告)日：2007-12-04

申请号：US09620649

申请日：2000-07-20

申请人： Cetin Kaya

发明人： Cetin Kaya

IPC分类号： H01L29/788 ,  H01L27/115

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/7881

摘要： The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the first intermediate structure comprising a floating gate layer disposed outwardly from the first dielectric layer, a second dielectric layer disposed outwardly from the floating gate layer, and a first polysilicon layer disposed outwardly from the second dielectric layer; (3) removing regions of the first intermediate structure to form at least one gate stack disposed outwardly from the first dielectric layer; and (4) forming at least one dielectric isolation region after the formation of the gate stacks, wherein the at least one dielectric isolation region is disposed between two gate stacks.

摘要翻译： 本发明包括形成集成电路的方法，该方法包括：（1）形成从半导体衬底向外设置的第一介电层; （2）从电介质层向外形成第一中间结构，所述第一中间结构包括从所述第一电介质层向外设置的浮动栅极层，从所述浮栅层向外设置的第二介电层和设置在所述第一多晶硅层 从第二介电层向外; （3）去除所述第一中间结构的区域以形成从所述第一介电层向外设置的至少一个栅极堆叠; 以及（4）在形成所述栅极叠层之后形成至少一个介电隔离区域，其中所述至少一个介电隔离区域设置在两个栅极叠层之间。

公开(公告)号：US06740905B1

公开(公告)日：2004-05-25

申请号：US10292150

申请日：2002-11-12

申请人： Cetin Kaya ,  Sreenath Unnikrishnan

发明人： Cetin Kaya ,  Sreenath Unnikrishnan

IPC分类号： H01L3300

CPC分类号： H01L27/14645 ,  H01L27/1463

摘要： The image sensor has improvements for suppressing cross talk without degrading red light response. This is accomplished by implanting a deep p+ layer 42 under blue and green pixels 24 and 22 but not under red pixels 20 in a standard RGB pattern color filter array.

摘要翻译： 图像传感器具有改进以抑制串扰而不降低红光响应。 这通过在标准RGB图案彩色滤光器阵列中的蓝色和绿色像素24和22而不是在红色像素20下方注入深p +层42来实现。

公开(公告)号：US06646925B2

公开(公告)日：2003-11-11

申请号：US10010413

申请日：2001-12-07

申请人： Cetin Kaya ,  Stephen K. Heinrich-Barna

发明人： Cetin Kaya ,  Stephen K. Heinrich-Barna

IPC分类号： G11C1604

CPC分类号： G11C16/14 ,  G11C16/16

摘要： A method for use in erasing data stored in a memory cell includes asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type. The method also includes floating the voltage level of a source region and a drain region of the memory cell, wherein the source region and the drain region are located within the tank region and have the second conductivity type. The method additionally includes discharging a charge stored in the drain region by electrically connecting the source region to an electric potential lower than the potential of the drain region and electrically connecting the well region and the tank region to a potential lower than their existing potentials.

公开(公告)号：US06194267B1

公开(公告)日：2001-02-27

申请号：US09168047

申请日：1998-10-07

申请人： Cetin Kaya

发明人： Cetin Kaya

IPC分类号： H01L2176

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/7881

摘要： The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the first intermediate structure comprising a floating gate layer disposed outwardly from the first dielectric layer, a second dielectric layer disposed outwardly from the floating gate layer, and a first polysilicon layer disposed outwardly from the second dielectric layer; (3) removing regions of the first intermediate structure to form at least one gate stack disposed outwardly from the first dielectric layer; and (4) forming at least one dielectric isolation region after the formation of the gate stacks, wherein the at least one dielectric isolation region is disposed between two gate stacks.

摘要翻译： 本发明包括形成集成电路的方法，该方法包括：（1）形成从半导体衬底向外设置的第一介电层; （2）从电介质层向外形成第一中间结构，所述第一中间结构包括从所述第一电介质层向外设置的浮动栅极层，从所述浮栅层向外设置的第二介电层和设置在所述第一多晶硅层 从第二介电层向外; （3）去除所述第一中间结构的区域以形成从所述第一介电层向外设置的至少一个栅极堆叠; 以及（4）在形成所述栅极叠层之后形成至少一个介电隔离区域，其中所述至少一个介电隔离区域设置在两个栅极叠层之间。

公开(公告)号：US5557565A

公开(公告)日：1996-09-17

申请号：US483423

申请日：1995-06-07

申请人： Cetin Kaya ,  Howard Tigelaar

发明人： Cetin Kaya ,  Howard Tigelaar

IPC分类号： G11C11/412 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C17/00 ,  G11C7/00

CPC分类号： G11C16/0425 ,  H01L29/42324 ,  H01L29/7885 ,  Y10S438/981

摘要： A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

摘要翻译： 可以仅使用五伏电源编程并且使用标准晶体管处理方法制造的非易失性分裂栅极存储单元8包括半导体衬底10，源极12和漏极14区域被沟道区域16分隔开 在沟道区域16的一部分16a上形成导电浮栅18，并由FAMOS氧化物20隔开。导电控制栅极22形成在与浮动栅极18之间并且在通道的第二部分16b之上并与其电绝缘 控制栅极22通过比FAMOS氧化物20厚的通过氧化物26与通道16b的第二部分分离。还公开了其它实施例和工艺。