公开(公告)号：US20110249504A1

公开(公告)日：2011-10-13

申请号：US12757399

申请日：2010-04-09

申请人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622

摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

摘要翻译： 在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。 在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。 该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。 集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。 在子脉冲组之后执行验证操作。 每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

公开(公告)号：US08036044B2

公开(公告)日：2011-10-11

申请号：US12504576

申请日：2009-07-16

申请人： Yingda Dong ,  Jun Wan

发明人： Yingda Dong ,  Jun Wan

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/16

摘要： Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.

摘要翻译： 通过自适应地调整擦除验证级别和程序验证级别来降低非易失性存储元件的降级。 确定完成擦除操作所需的擦除脉冲数或最高擦除脉冲幅度。 当数字或幅度达到极限时，擦除验证电平增加。 随着擦除验证电平的增加，所需擦除脉冲的数量减少，因为擦除操作可以更容易地完成。 从而避免了退化的加速增加。 一个或多个程序验证级别也可以随着擦除验证级别的变化而增加。 一个或多个程序验证电平可以增加与擦除验证电平相同的增量，以在擦除状态和编程状态之间维持恒定的阈值电压窗口，或者通过不同的增量。 提供了具有二进制或多级存储元素的实现。

公开(公告)号：US07995394B2

公开(公告)日：2011-08-09

申请号：US12512181

申请日：2009-07-30

申请人： Yingda Dong ,  Toru Ishigaki ,  Ken Oowada

发明人： Yingda Dong ,  Toru Ishigaki ,  Ken Oowada

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/3404

摘要： Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.

摘要翻译： 在所选择的字线的编程操作期间，在非易失性存储系统中，通过在与所选择的字线相邻的字线上最初使用具有较低幅度的通过电压来减少编程干扰。 这有助于减少浮栅边缘的电荷捕获，这可以通过增加编程擦除周期来扩大阈值电压分布。 当将较高幅度的编程脉冲施加到所选字线时，通过电压切换到较高电平以提供足够量的通道升压。 可以通过施加指定的编程脉冲或者通过跟踪下部状态存储元件直到达到目标验证电平来触发切换到较高通过电压。 当通过电压升高时，编程电压的幅度降低，从通过电压的变化中消除所选存储元件的电容耦合。

公开(公告)号：US20100329010A1

公开(公告)日：2010-12-30

申请号：US12490550

申请日：2009-06-24

申请人： Yingda Dong

发明人： Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483

摘要： A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases.

摘要翻译： 非存储元件的读操作补偿浮置栅极与浮置栅极耦合以及编程擦除周期的影响。 在字线WLn + 1的编程期间，WLn上预先编程的存储元件的阈值电压由于耦合而增加。 为了补偿增加，在WLn的后续读取操作期间，对施加到WLn的每个控制栅极读取电压，向WLn + 1施加不同的通过电压集合。 通过电压在每个不同的组中变化，使得它们是施加到WLn的控制栅极读取电压的函数。 通过电压也可以是编程擦除周期数的函数。 当编程擦除周期数增加时，通过增加通过电压来提供更高的补偿量。

公开(公告)号：US07800956B2

公开(公告)日：2010-09-21

申请号：US12163073

申请日：2008-06-27

申请人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

发明人： Dana Lee ,  Deepanshu Dutta ,  Yingda Dong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5621

摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.

摘要翻译： 在多遍编程过程中，非易失性存储器中的编程时间会减少。 在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。 一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。 此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。 在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。 与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

公开(公告)号：US07440323B2

公开(公告)日：2008-10-21

申请号：US11555850

申请日：2006-11-02

申请人： Jeffrey W. Lutze ,  Yingda Dong

发明人： Jeffrey W. Lutze ,  Yingda Dong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A method for operating a non-volatile storage system which reduces program disturb. Multiple boosting modes are implemented while programming non-volatile storage. For example, self-boosting, local self-boosting, erased area self-boosting and revised erased area self-boosting may be used. One or more switching criteria are used to determine when to switch to a different boosting mode. The boosting mode may be used to prevent program disturb in unselected NAND strings while storage elements are being programmed in selected NAND strings. By switching boosting modes, an optimal boosting mode can be used as conditions change. The boosting mode can be switched based on various criteria such as program pulse number, program pulse amplitude, program pass number, the position of a selected word line, whether coarse or fine programming is used, whether a storage element reaches a program condition and/or a number of program cycles of the non-volatile storage device.

摘要翻译： 一种用于操作减少程序干扰的非易失性存储系统的方法。 在编程非易失性存储时实现多种升压模式。 例如，可以使用自我增强，局部自我增强，消除区域自增强和修改的擦除区域自增强。 使用一个或多个切换标准来确定何时切换到不同的升压模式。 当存储元件被编程在所选择的NAND串中时，升压模式可用于防止未选择的NAND串中的程序干扰。 通过切换升压模式，可以在条件变化时使用最佳升压模式。 可以基于各种标准来切换升压模式，例如程序脉冲数，程序脉冲幅度，程序通过次数，所选字线的位置，是使用粗调还是精细编程，存储元件是否达到程序状态和/ 或非易失性存储设备的多个程序周期。

公开(公告)号：US20080137426A1

公开(公告)日：2008-06-12

申请号：US11609813

申请日：2006-12-12

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： Non-volatile storage with reduced program disturb is provided by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.

摘要翻译： 通过在阵列中升压未选择的NAND串来提供具有减少的编程干扰的非易失性存储器，使得在所选择的字线的源极侧上的源极通道在所选择的漏极侧的漏极侧之前被提升在漏极侧通道之前 字线。 在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。 在第一升压模式中，同时启动源极和漏极侧通道的升压。 当所选字线是较高字线时，使用第二升压模式。 在第二升压模式中，源极侧沟道的升压相对于漏极侧沟道的升压而早期发生。 升压模式包括易于将源极和漏极侧通道彼此隔离的隔离电压。

公开(公告)号：US20080137425A1

公开(公告)日：2008-06-12

申请号：US11609804

申请日：2006-12-12

申请人： Yingda Dong ,  Jeffrey W. Lutze

发明人： Yingda Dong ,  Jeffrey W. Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427 ,  G11C2211/565

摘要： Program disturb is reduced in non-volatile storage by boosting unselected NAND strings in an array so that a source side channel, on a source side of a selected word line, is boosted before a drain side channel, on a drain side of the selected word line. In one approach, a first boost mode is used when the selected word line is a lower or intermediate word line. In the first boost mode, boosting of the source and drain side channels is initiated concurrently. A second boost mode is used when the selected word line is a higher word line. In the second boost mode, boosting of the source side channel occurs early relative to the boosting of the drain side channel. Either boost mode include an isolation voltage which tends to isolate the source and drain side channels from one another.

摘要翻译： 在非易失性存储器中通过升高阵列中的未选择的NAND串来减少非易失性存储器中的编程干扰，使得在所选字线的漏极侧之前，在所选字线的源极侧的源极通道被提升在漏极侧通道之前 线。 在一种方法中，当所选字线是较低或中间字线时，使用第一升压模式。 在第一升压模式中，同时启动源极和漏极侧通道的升压。 当所选字线是较高字线时，使用第二升压模式。 在第二升压模式中，源极侧沟道的升压相对于漏极侧沟道的升压而早期发生。 升压模式包括易于将源极和漏极侧通道彼此隔离的隔离电压。

公开(公告)号：US08582381B2

公开(公告)日：2013-11-12

申请号：US13403934

申请日：2012-02-23

申请人： Ken Oowada ,  Yingda Dong ,  Gerrit Jan Hemink ,  Man Lung Mui ,  Hao Nguyen ,  Seungpil Lee ,  Jong Park ,  Fanglin Zhang

发明人： Ken Oowada ,  Yingda Dong ,  Gerrit Jan Hemink ,  Man Lung Mui ,  Hao Nguyen ,  Seungpil Lee ,  Jong Park ,  Fanglin Zhang

IPC分类号： G11C7/04 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3481 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028

摘要： A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

摘要翻译： 执行编程和读取过程的非易失性存储系统。 编程过程包括粗/精编程和验证操作。 通过测试两个不同的阈值电压电平来验证编程，同时通过测试存储器单元的电流水平并基于当前温度调整测试的电流水平，将相同的电压电平施加到存储器单元的控制栅极，使得 两个有效的测试阈值电压水平在温度变化上保持恒定。

公开(公告)号：US20130201760A1

公开(公告)日：2013-08-08

申请号：US13364518

申请日：2012-02-02

申请人： Yingda Dong ,  Man L. Mui ,  Hitoshi Miwa

发明人： Yingda Dong ,  Man L. Mui ,  Hitoshi Miwa

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/1157 ,  H01L27/11582

摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

摘要翻译： 用于3D堆叠存储器件的读取处理为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。 通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及 未选择的内存设备级别（Vcg_unsel）。 通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。 然后通过升高Vsgd_unsel和/或Vsgs_unsel使漏极侧和/或源极侧选择栅极变得不导通，从而中断升压。 此外，当Vcg_unsel仍在增加时，通过使漏极侧和/或源极选择栅极再次导通，可以发生升压。 或者，通道可以在Vbl驱动。 两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。