公开(公告)号：US06818948B2

公开(公告)日：2004-11-16

申请号：US10621597

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L2976

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A split gate flash memory device and method of fabricating the same. A cell of the split gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 一种分闸式闪存装置及其制造方法。 根据本发明的分裂栅极闪存器件的单元被布置在衬底内的单元沟槽中，以实现存储单元的更高集成度。

公开(公告)号：US06781191B2

公开(公告)日：2004-08-24

申请号：US10621431

申请日：2003-07-16

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L29788

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

公开(公告)号：US06770520B2

公开(公告)日：2004-08-03

申请号：US10436800

申请日：2003-05-13

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21337

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。 导电层的表面被图案化的硬掩模层覆盖以形成栅极。 使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。 导电层被氧化以在导电层的表面上形成氧化物层。 使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。

公开(公告)号：US06734066B2

公开(公告)日：2004-05-11

申请号：US10307704

申请日：2002-12-02

Applicant: Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

Inventor： Chi-Hui Lin ,  Jeng-Ping Lin ,  Pei-Ing Lee ,  Jih-Chang Lien

IPC: H01L21336

CPC classification number: H01L27/115 ,  H01L27/11553 ,  H01L29/42324 ,  H01L29/7885

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Abstract translation: 分闸门闪存单元。 存储单元包括基板，导线，源极/漏极区，绝缘层，导电间隔物，绝缘柱，第一导电层和第一绝缘间隔物。 导线设置在衬底的沟槽的下部。 源极区域形成在与其上具有绝缘层的导电线的上部相邻的衬底中。 导电间隔物设置在用作浮动栅极的沟槽的上侧壁上。 绝缘支柱设置在绝缘层上。 第一导电层设置在与用作控制栅极的导电间隔物相邻的衬底上。 第一绝缘间隔件设置在绝缘螺柱的侧壁上以覆盖第一导电层。 漏极区域形成在与第一导电层相邻的衬底中。

公开(公告)号：US06562673B2

公开(公告)日：2003-05-13

申请号：US09948530

申请日：2001-09-07

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L218238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating a memory cell of self-aligned split gate flash memory first provides a substrate having an active area. A first gate insulating layer, a conductive layer and a buffer layer are formed within the active area. A portion of the buffer layer is removed to form a first opening. A buffer spacer is formed on the side walls of the first opening. A portion of the conductive layer and first gate insulating layer under the first opening are removed to form a second opening. The contact spacers, the source region and the contact plug are formed in the second opening in sequence. After the buffer spacers are removed, a third opening is formed. The bottom surface of the third opening and the top surface of the contact plug are oxidized to form the oxide layers. Another buffer spacers fill the third opening. The remaining buffer layer is removed to form the fourth opening. The conductive layer under the bottom of the fourth opening is removed, except the portion under the oxide layer, to form the floating gates. After the formation of a second gate insulating layer, the control gates and the control gate spacers are formed in sequence.

公开(公告)号：US06511881B1

公开(公告)日：2003-01-28

申请号：US10191722

申请日：2002-07-08

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for fabricating split gate flash memory cell. The method includes sequentially forming conductive layers and insulating layers on a semiconductor substrate, followed by forming a first opening in the conductive layers and the insulating layers. Next, a shallow trench isolation is defined in the first opening and an insulating layer is defined simultaneously in the active area within the shallow trench isolation to form a first gate isolation layer. Then, a conductive sidewall layer is formed on the sidewalls of the first gate insulating layer. The first gate insulating layer and the conductive sidewall layer are used as a hard mask to remove the conductive layer not covered by the hard mask, thus forming a floating gate comprised of the conductive sidewall layer and the conductive layer underneath. A second gate insulating layer, control gate and source/drain are then formed conventionally.

Abstract translation: 一种用于制造分流栅闪存单元的方法。 该方法包括在半导体衬底上依次形成导电层和绝缘层，随后在导电层和绝缘层中形成第一开口。 接下来，在第一开口中限定浅沟槽隔离，并且在浅沟槽隔离中的有源区域中同时限定绝缘层，以形成第一栅极隔离层。 然后，在第一栅极绝缘层的侧壁上形成导电侧壁层。 第一栅绝缘层和导电侧壁层用作硬掩模以去除未被硬掩模覆盖的导电层，从而形成由导电侧壁层和下面的导电层组成的浮栅。 然后通常形成第二栅极绝缘层，控制栅极和源极/漏极。

公开(公告)号：US07056792B2

公开(公告)日：2006-06-06

申请号：US10819464

申请日：2004-04-06

Applicant: Chi-Hui Lin

Inventor： Chi-Hui Lin

IPC: H01L21/336

CPC classification number: H01L27/11556 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract translation: 堆叠式栅极闪存器件及其制造方法。 根据本发明的堆叠式栅极闪存器件的单元被布置在衬底内的单元沟槽中以实现存储单元的更高集成度。

公开(公告)号：US06921694B2

公开(公告)日：2005-07-26

申请号：US10442308

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract translation: 一种用于制造具有多个尖端的浮动栅极的方法。 提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。 图案化的硬掩模层具有露出半导体衬底的表面的开口。 在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。 导电层被平坦化以暴露图案化的硬掩模层的表面。 导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。

公开(公告)号：US20050127422A1

公开(公告)日：2005-06-16

申请号：US10707396

申请日：2003-12-10

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract translation: 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US06870216B2

公开(公告)日：2005-03-22

申请号：US10606702

申请日：2003-06-26

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/72

CPC classification number: H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7881

Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.

Abstract translation: 堆叠式门垂直闪存及其制造方法。 层叠栅极垂直闪速存储器包括具有沟槽的半导体衬底，形成在沟槽底部的源极导电层，形成在源极导电层上的绝缘层，形成在沟槽侧壁上的栅极电介质层，导电层 覆盖作为浮动栅极的栅极介电层的隔板，覆盖导电间隔物的栅极间介电层和填充在沟槽中的控制栅极导电层。