公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US08551881B2

公开(公告)日：2013-10-08

申请号：US13093735

申请日：2011-04-25

申请人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44

CPC分类号： H01L21/304 ,  H01L21/76898

摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

摘要翻译： 公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的 边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

公开(公告)号：US08487397B2

公开(公告)日：2013-07-16

申请号：US13093742

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

摘要翻译： 具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。 晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。 电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。 保护屏障形成在电介质间隔物上。 导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

公开(公告)号：US20130099309A1

公开(公告)日：2013-04-25

申请号：US13281293

申请日：2011-10-25

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

摘要翻译： 公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域， 以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

公开(公告)号：US08415729B2

公开(公告)日：2013-04-09

申请号：US13081500

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/66348

摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

摘要翻译： 具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域 设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中， 以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。 波浪形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。

公开(公告)号：US20130078815A1

公开(公告)日：2013-03-28

申请号：US13244013

申请日：2011-09-23

申请人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/3065

CPC分类号： H01L21/31116 ,  B23K10/003 ,  B23K2101/40

摘要： A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency.

摘要翻译： 提供了一种形成具有线边缘粗糙度降低的半导体结构的方法，包括：提供其上形成有图案化光致抗蚀剂层的器件层; 以及执行等离子体蚀刻工艺以对其上形成有图案化的光致抗蚀剂层进行图案化，形成图案化的器件层，其中等离子体蚀刻工艺在具有相对较高频率和开关的连续的阶段电压下操作 脉冲调制的阶段电压具有相对较低的频率。

公开(公告)号：US20130071978A1

公开(公告)日：2013-03-21

申请号：US13236656

申请日：2011-09-20

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/66606 ,  H01L21/28044 ,  H01L29/66553 ,  H01L29/78

摘要： A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.

摘要翻译： 提供晶体管的制造方法。 图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。 通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。 执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。 去除图案化牺牲层以暴露源极和漏极之间的衬底。 栅极形成在源极和漏极之间的衬底上。

公开(公告)号：US20130062727A1

公开(公告)日：2013-03-14

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US20130045600A1

公开(公告)日：2013-02-21

申请号：US13210172

申请日：2011-08-15

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/308

CPC分类号： H01L29/7854 ,  H01L29/7853

摘要： A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.

摘要翻译： 提供了一种制造鳍状半导体结构的方法，包括：提供半导体衬底和形成在其上的介电层的半导体衬底; 在所述半导体岛和所述电介质层上形成掩模层; 在所述掩模层中形成开口，使所述半导体岛的上表面和与所述半导体岛相邻的所述电介质层的部分露出; 进行蚀刻处理，同时蚀刻掩模层的一部分，以及由开口暴露的半导体岛和电介质层的部分; 并且去除掩模层和电介质层，在半导体衬底上留下具有弯曲顶表面和各种厚度的蚀刻半导体岛。

公开(公告)号：US08367509B1

公开(公告)日：2013-02-05

申请号：US13239030

申请日：2011-09-21

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76897

摘要： A method for forming a contact of a semiconductor device with reduced step height is disclosed, comprising forming a plurality of gates, forming a buffer layer on each of the gates, forming an insulating layer to fill spaces between the gates, forming strip-shaped photoresist patterns which cross the gates, etching the insulating layer to form first openings using a self-aligning process with the gates and the strip-shaped photoresist patterns as a mask, forming a conductive contact layer to fill the first openings, performing a first chemical mechanical polish (CMP) process to the conductive contact layer, removing the buffer layer, and forming a second chemical mechanical polish (CMP) process to the conductive contact layer.

摘要翻译： 公开了一种用于形成具有降低的台阶高度的半导体器件的接触的方法，包括形成多个栅极，在每个栅极上形成缓冲层，形成绝缘层以填充栅极之间的空间，形成带状光致抗蚀剂 通过栅极和带状光致抗蚀剂图案作为掩模蚀刻绝缘层以形成第一开口，形成导电接触层以填充第一开口，执行第一化学机械 抛光（CMP）工艺到导电接触层，去除缓冲层，以及对导电接触层形成第二化学机械抛光（CMP）工艺。