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    Circuit board device and a combined circuit board and electronic card assembly
    11.
    发明授权
    Circuit board device and a combined circuit board and electronic card assembly 有权
    电路板装置和组合电路板和电子卡组件

    公开(公告)号：US08764457B2

    公开(公告)日：2014-07-01

    申请号：US13585070

    申请日：2012-08-14

    Applicant: Chih-Ping Chen ,  Ping-Yu Ko

    Inventor： Chih-Ping Chen ,  Ping-Yu Ko

    IPC: H01R12/00 ,  H05K7/02

    CPC classification number: H05K7/142

    Abstract: A circuit board device for fixing an electronic card, which is formed with at least one aperture, includes a circuit board and a securing member. The circuit board includes a board body formed with two through holes, and a socket connector provided on the board body for mating with the electronic card. The securing member includes a pressing plate for pressing against the electronic card, at least one engaging stud projecting from a bottom end of the pressing plate for engaging the aperture, and two resilient engaging arms provided respectively on left and right sides of the pressing plate. The engaging arms extend respectively through the through holes and engage releasably the board body.

    Abstract translation: 用于固定形成有至少一个孔的电子卡的电路板装置包括电路板和固定构件。 电路板包括形成有两个通孔的电路板主体和设置在电路板主体上用于与电子卡匹配的插座连接器。 固定构件包括用于按压电子卡片的按压板，从按压板的底端突出的用于接合孔的至少一个接合柱，以及分别设置在按压板的左侧和右侧的两个弹性接合臂。 接合臂分别延伸穿过通孔并可释放地接合板体。

    Storing mechanism
    15.
    发明授权
    Storing mechanism 失效
    存储机制

    公开(公告)号：US07529084B2

    公开(公告)日：2009-05-05

    申请号：US11309207

    申请日：2006-07-13

    Applicant: Hung-Ta Liao ,  Chih-Ping Chen ,  Ku-Feng Chen

    Inventor： Hung-Ta Liao ,  Chih-Ping Chen ,  Ku-Feng Chen

    IPC: H05K5/00 ,  H05K7/00 ,  G06F1/16

    CPC classification number: G11B17/043

    Abstract: A storing mechanism suitable for being disposed in an electronic device is provided, which is used to store a first hard disk with a first thickness or a second hard disk with a second thickness. The storing mechanism includes a first module, a second module and a restoring element. The first module includes a base and a lever. The lever having a leaned portion is pivoted to the base. Additionally, the second module includes a tray and a slide. The tray is glidingly disposed on the base, and has a stopper for being limited to the leaned portion, so as to limit the shift of the tray relative to the base. The slide is glidingly disposed on the tray. Moreover, the restoring element is disposed between the base and the tray for making the delocalized tray move back to the original location.

    Abstract translation: 提供一种适用于设置在电子设备中的存储机构，其用于存储具有第二厚度的具有第一厚度的第一硬盘或第二硬盘。 存储机构包括第一模块，第二模块和恢复元件。 第一模块包括底座和杠杆。 具有倾斜部分的杠杆枢转到基座。 另外，第二模块包括托盘和滑块。 托盘滑动地设置在基座上，并且具有限制在倾斜部分上的止动件，以便限制托盘相对于底座的移动。 幻灯片滑动地放置在托盘上。 此外，恢复元件设置在基座和托盘之间，以使离域托盘移回到原始位置。

    Management of watchpoints in debuggers
    16.
    发明申请
    Management of watchpoints in debuggers 有权
    管理调试器中的观察点

    公开(公告)号：US20070079292A1

    公开(公告)日：2007-04-05

    申请号：US11241606

    申请日：2005-09-30

    Applicant: Chih-Ping Chen ,  Jeffrey Olivier ,  Jay Hoeflinger ,  Bevin Brett

    Inventor： Chih-Ping Chen ,  Jeffrey Olivier ,  Jay Hoeflinger ,  Bevin Brett

    IPC: G06F9/44

    CPC classification number: G06F11/362

    Abstract: Provided are a method, system, and article of manufacture, wherein a first application requests an operating system to monitor a memory address, and wherein the operating system generates a signal in response to an operation that affects the memory address. A second application receives the generated signal. The second application determines whether to forward the signal to the first application. The first application processes the signal, in response to the signal being forwarded by the second application.

    Abstract translation: 提供了一种方法，系统和制品，其中第一应用请求操作系统监视存储器地址，并且其中操作系统响应于影响存储器地址的操作来生成信号。 第二个应用程序接收所产生的信号。 第二个应用程序确定是否将信号转发到第一个应用程序。 响应于由第二应用转发的信号，第一应用处理该信号。

    Critical dimension statistical process control in semiconductor fabrication
    17.
    发明授权
    Critical dimension statistical process control in semiconductor fabrication 有权
    半导体制造中的关键维度统计过程控制

    公开(公告)号：US06799152B1

    公开(公告)日：2004-09-28

    申请号：US10206268

    申请日：2002-07-26

    Applicant: Chih-Ping Chen ,  Shao-Chung Hsu ,  De-Chuan Liu ,  Jung-Kuei Lu ,  Cheng-Yi Lin ,  Ta-Hung Yang ,  Hsin-Cheng Liu ,  Mao-I Ting ,  Yih-Cheng Shih

    Inventor： Chih-Ping Chen ,  Shao-Chung Hsu ,  De-Chuan Liu ,  Jung-Kuei Lu ,  Cheng-Yi Lin ,  Ta-Hung Yang ,  Hsin-Cheng Liu ,  Mao-I Ting ,  Yih-Cheng Shih

    IPC: G06F1750

    CPC classification number: G06F17/50 ,  G06F2217/10 ,  G07C3/146

    Abstract: The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

    Abstract translation: 本发明提供了一种用于分析在集成电路制造期间发生的工艺变化的方法。 针对集成电路制造过程的每个层收集关键尺寸数据一段时间，并且计算指示集成电路制造过程的每层的临界尺寸数据的变化的移位指示器。 还针对在集成电路制造工艺的每个层中使用的每个机器计算机器漂移显着性指标，并且定义了集成电路制造工艺的每一层的平均值的最大偏移。 移位指示器，平均值的最大偏移和机器漂移显着性指示器用于确定集成电路制造过程的每个层的关键尺寸的至少一个可能的变化原因。

    Method of fabricating read only memory
    18.
    发明授权
    Method of fabricating read only memory 有权

    公开(公告)号：US06569713B2

    公开(公告)日：2003-05-27

    申请号：US09881819

    申请日：2001-06-15

    Applicant: Chih-Ping Chen

    Inventor： Chih-Ping Chen

    IPC: H01L2182

    CPC classification number: H01L27/1126 ,  H01L27/112

    Abstract: A method of fabricating a read only memory. After forming bit lines and word lines in a substrate, a coding process is performed. A photoresist layer is formed on the substrate while performing the coding process. The photoresist layer covering a part of a first channel region under the word line is exposed, and then the photoresist layer covering a part of a second channel region under the word lines is exposed. A development step is performed to remove the photoresist layer that has been exposed. Using the remaining photoresist layer as a mask to perform an ion implantation, a coding area is formed in the first channel region and the second channel region. The photoresist layer is removed.

    Procedure of alignment for optimal wafer exposure pattern
    19.
    发明授权
    Procedure of alignment for optimal wafer exposure pattern 有权
    对准最佳晶片曝光图案的步骤

    公开(公告)号：US06368761B1

    公开(公告)日：2002-04-09

    申请号：US09568323

    申请日：2000-05-09

    Applicant: Chen-Fu Chien ,  Shao-Chung Hsu ,  Chih-Ping Chen

    Inventor： Chen-Fu Chien ,  Shao-Chung Hsu ,  Chih-Ping Chen

    IPC: G03F900

    CPC classification number: G03F9/7084 ,  G03F7/70433 ,  G03F9/7046

    Abstract: Conventionally, efforts to improve the yield of chips produced on a wafer focused on defect reduction. Another approach is optimizing wafer exposure patterns. The present invention includes a computer-based procedure and apparatus to expose cells on the surface of a wafer so as to maximize the number of dies produced from a wafer. The invention is useful in the exposure of six and eight inch wafers, as well as larger wafers.

    Abstract translation: 通常，提高晶片上产生的芯片的产量的努力集中在缺陷减少。 另一种方法是优化晶片曝光模式。 本发明包括一种基于计算机的程序和装置，用于暴露晶片表面上的单元，从而最大化从晶片产生的模具的数量。 本发明可用于六和八英寸晶片以及较大晶片的曝光。

    Voltage regulator with power saving function
    20.
    发明授权
    Voltage regulator with power saving function 有权
    电压调节器具有省电功能

    公开(公告)号：US08686707B2

    公开(公告)日：2014-04-01

    申请号：US13297279

    申请日：2011-11-16

    Applicant: Yu-Pao Kung ,  Chih-Ping Chen

    Inventor： Yu-Pao Kung ,  Chih-Ping Chen

    IPC: G05F3/04 ,  G05F1/00

    CPC classification number: G05F1/575

    Abstract: A voltage regulator with a low quiescent current is provided. The voltage regulator includes a pulse voltage generating unit, a first switch unit, a regulating unit and a power output unit. The pulse voltage generating unit receives an input voltage to provide an intermittent signal with a predetermined period, and output a pulse voltage according to the intermittent signal. The first switch unit is turned on according to the intermittent signal. The regulating unit converts the pulse voltage into a continuous voltage. The power output unit receives the continuous voltage to output a voltage power through a power output terminal. And, the power output unit detects an output current of the power output terminal to adjust current drive capability of the power output unit dynamically. Thus, the pulse voltage generating unit consumes power while the intermittent signal is enabled, so as to achieve the power saving effect.

    Abstract translation: 提供具有低静态电流的电压调节器。 电压调节器包括脉冲电压产生单元，第一开关单元，调节单元和功率输出单元。 脉冲电压产生单元接收输入电压以提供具有预定周期的间歇信号，并且根据间歇信号输出脉冲电压。 第一开关单元根据间歇信号接通。 调节单元将脉冲电压转换为连续电压。 电力输出单元接收连续电压，通过电力输出端子输出电压电力。 并且，电力输出单元检测电力输出端子的输出电流，动态地调整电力输出单元的电流驱动能力。 因此，脉冲电压产生单元在间歇信号使能的同时消耗电力，从而达到省电效果。

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