公开(公告)号：US06432794B1

公开(公告)日：2002-08-13

申请号：US09538911

申请日：2000-03-30

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2120

CPC分类号： H01L28/60 ,  H01L21/2885 ,  H01L21/76885 ,  H01L28/55 ,  H01L28/75

摘要： A process for fabricating a capacitor suitable for forming a bottom electrode layer of the capacitor on a substrate. First, a first dielectric layer is formed on a substrate. Then, a portion of the first dielectric layer is removed to form a contact hole. A conductive plug is formed within the contact hole. A seed layer is formed on the conductive plug. A sacrifice layer is formed on both the seed layer and the first dielectric layer. A predetermined region of the sacrifice layer is removed to form a recess so as to expose the seed layer. Then, a bottom electrode layer is formed by electroplating within the recess. The sacrifice layer is removed afterwards. Finally, a second dielectric layer and a top electrode layer are formed on the bottom electrode layer in sequence. The present invention is characterized in that it does not require a direct etching process on a platinum material to. form the bottom electrode layer. As a result, problems encountered during the platinum etching process such as the difficulty in controlling the critical dimension of an etched platinum bottom electrode layer can be overcome.

摘要翻译： 一种用于制造适于在基板上形成电容器的底电极层的电容器的工艺。 首先，在基板上形成第一电介质层。 然后，去除第一电介质层的一部分以形成接触孔。 导电插塞形成在接触孔内。 种子层形成在导电插头上。 牺牲层形成在种子层和第一介电层两者上。 去除牺牲层的预定区域以形成凹部以暴露种子层。 然后，通过在凹部内电镀形成底部电极层。 牺牲层之后被去除。 最后，依次在底电极层上形成第二电介质层和顶电极层。 本发明的特征在于不需要对铂材料进行直接蚀刻处理。 形成底部电极层。 结果，可以克服在铂蚀刻工艺期间遇到的难以控制蚀刻的铂底部电极层的临界尺寸的问题。

公开(公告)号：US06417066B1

公开(公告)日：2002-07-09

申请号：US09783380

申请日：2001-02-15

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2120

CPC分类号： H01L28/88 ,  H01L28/84

摘要： A process for fabricating a fin type, cylindrical shaped, DRAM capacitor structure, with increased surface area, has been developed. The process features forming a non-continuous layer of discrete regions of silicon, on the surface of a capacitor opening, in a composite insulator layer. The discrete regions of silicon are then used as an etch mask to allow an isotropic etching procedure to create horizontal channels in the sides of the portions of the composite insulator layer exposed in the capacitor opening, creating a capacitor opening comprised with horizontal channnels. An amorphous silicon layer is then deposited and patterned to form a fin type, storage node structure, comprised of amorphous silicon on discrete regions of silicon, in the capacitor opening. Formation of a capacitor dielectric layer, and an overlying top electrode structure, complete the formation of a fin type, cylindrical shaped, DRAM capacitor structure.

摘要翻译： 已经开发了用于制造具有增加的表面积的翅片型圆柱形DRAM电容器结构的工艺。 该工艺在复合绝缘体层中在电容器开口的表面上形成非连续层的离散区域的硅层。 然后将硅的离散区域用作蚀刻掩模，以允许各向同性蚀刻程序在暴露在电容器开口中的复合绝缘体层的部分的侧面中产生水平通道，从而产生包括水平通道的电容器开口。 然后沉积非晶硅层并将其图案化以形成在电容器开口中由硅的离散区域上的非晶硅组成的鳍式存储节点结构。 形成电容器电介质层和上覆电极结构，完成鳍型圆柱形DRAM电容器结构的形成。

公开(公告)号：US06413856B1

公开(公告)日：2002-07-02

申请号：US09414817

申请日：1999-10-08

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L2221/1036

摘要： A method of forming dual damascene structure is disclosed. A pad oxide layer, a barrier layer and an organic dielectric layer are formed in sequence on a substrate with the conducting line and the organic dielectric layer is etched with a patterned photoresist as a mask to form trenches therein. Next, an anisotropic thickness oxide layer is formed on the substrate by the plasma enhanced chemical vapor deposition (PECVD). Then, the anisotropic thickness oxide layer, the barrier layer and the pad oxide layer are etched with a patterned photoresist as a mask to form vias therein until the conducting line is exposed. Finally, a metal layer is deposited on the substrate and fills the vias and the trenches to form the dual damascene structure.

摘要翻译： 公开了一种形成双镶嵌结构的方法。 在衬底上依次形成衬垫氧化物层，阻挡层和有机电介质层，并且用图案化的光致抗蚀剂作为掩模蚀刻有机介电层，以在其中形成沟槽。 接下来，通过等离子体增强化学气相沉积（PECVD）在衬底上形成各向异性厚度氧化物层。 然后，用图案化的光致抗蚀剂作为掩模蚀刻各向异性厚度氧化物层，势垒层和焊盘氧化物层，以在其中形成通孔，直到导电线暴露。 最后，将金属层沉积在衬底上并填充通孔和沟槽以形成双镶嵌结构。

公开(公告)号：US06291333B1

公开(公告)日：2001-09-18

申请号：US09557510

申请日：2000-04-25

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/7681 ,  H01L21/76831 ,  H01L23/485 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a dual damascene structure. The method forms a silicon oxide layer, a stop layer, a low k organic dielectric layer, and a cap layer are formed in sequence on a substrate. A trench is formed in the cap layer and the low k organic dielectric layer, while a via opening is formed in the stop layer and the silicon oxide layer. A part of the stop layer is removed to form a cavity below the low k organic dielectric layer, followed by forming fluorinated poly-arlyethers spacers on sidewalls of the trench and the via opening which fills the cavity. The trench and the via opening are then filled with a copper layer to form a dual damascene structure.

摘要翻译： 一种制造双镶嵌结构的方法。 该方法在衬底上依次形成氧化硅层，停止层，低k有机介电层和覆盖层。 在盖层和低k有机介电层中形成沟槽，同时在停止层和氧化硅层中形成通孔。 去除阻挡层的一部分以在低k有机介电层下面形成空腔，随后在沟槽的侧壁上形成氟化聚芳醚隔离物，填充空腔的通孔开口。 然后用铜层填充沟槽和通孔开口以形成双镶嵌结构。

公开(公告)号：US06239020B1

公开(公告)日：2001-05-29

申请号：US09429190

申请日：1999-10-28

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L27/10894 ,  H01L27/10897

摘要： A method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region is described, wherein semiconductor devices are formed on the memory cell region and the periphery circuit region so as to result in a height variation therebetween. The present method comprises the steps of forming a first dielectric layer blanket-covering the semiconductor substrate, wherein a first height variation exists between the memory cell region and the periphery circuit region. Then, a stop layer is conformally blanket formed on the first dielectric layer. Next, a second dielectric layer is conformally formed on the stop layer. A chemical mechanical polishing process is executed on the second dielectric layer until the stop layer on the memory cell region is exposed. This formation of the structure of a first dielectric layer/stop layer/second dielectric layer is repeated at least two times to achieve a planarized interlayer dielectric layer. A cap layer is formed on the top surface of the planarized interlayer dielectric layer.

摘要翻译： 描述了在具有存储单元区域和外围电路区域的半导体衬底上制造层间电介质层的方法，其中半导体器件形成在存储单元区域和外围电路区域上，从而导致其间的高度变化。 本方法包括以下步骤：形成覆盖半导体衬底的第一介电层，其中在存储单元区域和外围电路区域之间存在第一高度变化。 然后，在第一电介质层上保形地形成阻挡层。 接下来，在停止层上保形地形成第二电介质层。 在第二电介质层上执行化学机械抛光工艺，直到存储单元区域上的停止层被暴露。 将第一介电层/停止层/第二介质层的结构的这种形成重复至少两次以实现平坦化的层间电介质层。 在平坦化层间电介质层的顶表面上形成覆盖层。

公开(公告)号：US06235625B1

公开(公告)日：2001-05-22

申请号：US09335553

申请日：1999-06-18

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L214763

CPC分类号： H01L21/76855 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76879

摘要： A method of fabricating a Cu damascene, the method comprises of forming an amorphous silicon layer in a trench line and a via. The amorphous silicon layer is then displaced with a Cu layer using a Cu displacement process. With the Cu layer serving as a seeding layer, a Cu electroplating or a Cu electroless plating is performed, so that the trench line and the via is selectively filled with the Cu layer.

摘要翻译： 一种制造Cu镶嵌体的方法，所述方法包括在沟槽线和通孔中形成非晶硅层。 然后使用Cu置换方法用Cu层移位非晶硅层。 在Cu层作为接种层的情况下，进行Cu电镀或Cu化学镀，使得沟槽线和通孔被选择性地填充Cu层。

公开(公告)号：US06200881B1

公开(公告)日：2001-03-13

申请号：US09359415

申请日：1999-07-23

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： The present discloses a method of forming shallow trench isolation to prevent the dishing effect, the corner effect and provide an effective endpoint detection. The method includes these steps below. A pad oxide layer is formed on a semiconductor substrate. A first silicon nitride layer is formed on the pad oxide layer. A trench is formed in the substrate. A liner layer is formed on sidewalls and a bottom of the trench. A second silicon nitride layer is formed on the first silicon nitride layer and the liner layer. A polysilicon layer is formed on the second silicon nitride layer. A first silicon dioxide layer is formed on said polysilicon layer, thereby filling the trench with the first silicon dioxide layer. The first silicon dioxide layer is polished by performing a chemical mechanical polishing with a poly slurry. The polysilicon layer is oxidized to form a second silicon dioxide layer. The first silicon nitride layer and the second silicon nitride layer are removed. Silicon nitride spacers are formed on corners of the silicon dioxide protrusion and the second silicon dioxide layer. The pad oxide layer is removed. Finally, the silicon nitride spacers are removed.

摘要翻译： 本发明公开了一种形成浅沟槽隔离以防止凹陷效应，拐角效应并提供有效端点检测的方法。 该方法包括以下步骤。 在半导体衬底上形成焊盘氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 在衬底中形成沟槽。 衬里层形成在沟槽的侧壁和底部上。 在第一氮化硅层和衬垫层上形成第二氮化硅层。 在第二氮化硅层上形成多晶硅层。 在所述多晶硅层上形成第一二氧化硅层，由此用第一二氧化硅层填充沟槽。 通过用聚浆料进行化学机械抛光来抛光第一二氧化硅层。 多晶硅层被氧化以形成第二二氧化硅层。 去除第一氮化硅层和第二氮化硅层。 氮化硅间隔物形成在二氧化硅突起和第二二氧化硅层的角上。 去除衬垫氧化物层。 最后，去除氮化硅间隔物。

公开(公告)号：US06200852B1

公开(公告)日：2001-03-13

申请号：US09393705

申请日：1999-09-10

申请人： Chine-Gie Lou ,  Min-Hwa Chi

发明人： Chine-Gie Lou ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L21/3185 ,  H01L27/1085 ,  H01L28/56

摘要： A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700° C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.

摘要翻译： 公开了一种用于制造具有高介电常数的DRAM电容器介电层的方法。 在第一优选实施例中，工艺温度为约700℃或更低。 因此，本实施例适用于具有金属硅化物晶体管的DRAM。 在这些工艺中，在各个薄膜表面上形成多个薄的氮化硅层，以获得不匹配的电介质层的针孔缺陷。 在第二优选实施方案中，该方法使用不同的CVD方法沉积多个薄的氮化硅层，因此针孔缺陷是不匹配的。 两个实施例都提供具有最小漏电流的电容器电介质层，以增加电容。

公开(公告)号：US06174769B1

公开(公告)日：2001-01-16

申请号：US09335547

申请日：1999-06-18

申请人： Chine-Gie Lou

发明人： Chine-Gie Lou

IPC分类号： H01L218242

CPC分类号： H01L28/82 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/87 ,  H01L28/91

摘要： A method for manufacturing stacked capacitor. The method utilizes a manufacture method of a trench line and a via applied in dual damascene process to form a trench line and a via in a dielectric layer. Then, multi-amorphous silicon layers with different doping concentration are conformally formed on an exposed surface of the trench line and the via to serve as a bottom electrode of a double-sided double-crown-shaped capacitor. Furthermore, a phosphine (PH3) treatment process is performed after hemispherical grains are formed on the bottom electrode of the double-sided double-crown-shaped capacitor to increase the doping concentration of the bottom electrode surface of the capacitor. Moreover, a poly slurry having a high polishing selectivity of amorphous silicon to silicon nitride is used in a chemical mechanical polishing process during the formation of the double-sided double-crown-shaped capacitor to promote good uniformity of the polished wafer and make the polish end point available.

摘要翻译： 叠层电容器的制造方法。 该方法利用在双镶嵌工艺中应用的沟槽线和通孔的制造方法，以在电介质层中形成沟槽线和通孔。 然后，在沟槽线和通孔的暴露表面上共形形成具有不同掺杂浓度的多非晶硅层，以用作双面双冠状电容器的底部电极。 此外，在双面双冠状电容器的底部电极上形成半球形晶粒之后，进行磷化氢（PH3）处理工艺，以增加电容器的底部电极表面的掺杂浓度。 此外，在双面双冠形电容器的形成期间，在化学机械抛光工艺中使用具有高非晶硅与氮化硅的抛光选择性的聚浆料，以促进抛光晶片的良好均匀性并使抛光 终点可用。

公开(公告)号：US08232659B2

公开(公告)日：2012-07-31

申请号：US12048015

申请日：2008-03-13

申请人： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

发明人： Hsueh-Chung Chen ,  Chine-Gie Lou ,  Su-Chen Fan

IPC分类号： H01L23/544 ,  H01L23/34

CPC分类号： H01L21/681

摘要： Alignment methods of IC device substrates. A first IC device substrate has a first front side for defining a plurality of first IC features, a first backside opposite the first front side, and a first alignment pattern formed on the first front side or the first backside. A second IC device substrate has a second front side for defining a plurality of second IC features, a second backside opposite the second front side, and a second alignment pattern formed on the second front side or the second backside. A first optical detector and a second optical detector are applied to detect the first and second alignment patterns, so as to align the first and second IC device substrates. Specifically, the first and second alignment patterns face toward the first and second optical detectors in opposite directions.

摘要翻译： IC器件基板的对准方法。 第一IC器件衬底具有用于限定多个第一IC特征的第一前侧，与第一前侧相对的第一背面，以及形成在第一前侧或第一背面上的第一对准图案。 第二IC器件衬底具有用于限定多个第二IC特征的第二前侧，与第二前侧相对的第二后侧和形成在第二前侧或第二后侧上的第二对准图案。 应用第一光学检测器和第二光学检测器来检测第一和第二对准图案，以对准第一和第二IC器件基板。 具体地，第一和第二对准图案朝向相反方向的第一和第二光学检测器。