公开(公告)号：US06200852B1

公开(公告)日：2001-03-13

申请号：US09393705

申请日：1999-09-10

申请人： Chine-Gie Lou ,  Min-Hwa Chi

发明人： Chine-Gie Lou ,  Min-Hwa Chi

IPC分类号： H01L218242

CPC分类号： H01L21/3185 ,  H01L27/1085 ,  H01L28/56

摘要： A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700° C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.

摘要翻译： 公开了一种用于制造具有高介电常数的DRAM电容器介电层的方法。 在第一优选实施例中，工艺温度为约700℃或更低。 因此，本实施例适用于具有金属硅化物晶体管的DRAM。 在这些工艺中，在各个薄膜表面上形成多个薄的氮化硅层，以获得不匹配的电介质层的针孔缺陷。 在第二优选实施方案中，该方法使用不同的CVD方法沉积多个薄的氮化硅层，因此针孔缺陷是不匹配的。 两个实施例都提供具有最小漏电流的电容器电介质层，以增加电容。

公开(公告)号：US09012286B2

公开(公告)日：2015-04-21

申请号：US13445428

申请日：2012-04-12

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L21/823821 ,  H01L29/1054 ,  H01L29/66818

摘要： Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

摘要翻译： 本文公开了形成FinFET半导体器件的各种方法，以调谐这些器件的阈值电压。 在一个示例中，该方法包括在半导体衬底内形成多个间隔开的沟槽，以在形成鳍片（或鳍片）之上的栅极结构之前，为器件限定至少一个翅片（或鳍片），执行第一 外延生长工艺以在翅片（或翅片）的暴露部分上生长第一半导体材料，并在翅片（或翅片）上的第一半导体材料上方形成栅极结构。

公开(公告)号：US08362528B2

公开(公告)日：2013-01-29

申请号：US12611360

申请日：2009-11-03

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L27/088

CPC分类号： H01L29/66477 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/7392

摘要： A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

公开(公告)号：US08208286B2

公开(公告)日：2012-06-26

申请号：US12861622

申请日：2010-08-23

申请人： Min-Hwa Chi ,  Deyuan Xiao

发明人： Min-Hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  G11C11/36 ,  H01L21/02

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US07804155B2

公开(公告)日：2010-09-28

申请号：US12358347

申请日：2009-01-23

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L29/66

CPC分类号： H01L27/0802 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8605

摘要： A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.

摘要翻译： 一个垂直电阻。 衬底包括由隔离层填充的沟槽。 第一掺杂型区域和第二掺杂型区域形成在沟槽的两侧。 第一掺杂型区域接收控制偏压，第二掺杂型区域接收参考偏置，并且响应于控制偏压和参考电压之间的电压差来调整第二掺杂型区域和衬底之间的电阻 偏压。

公开(公告)号：US07737532B2

公开(公告)日：2010-06-15

申请号：US11220176

申请日：2005-09-06

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

摘要翻译： 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 表示包括{l，m，n}的米勒指数族，其中l2 + m2 + n2> i2 + j2 + k2。 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US07709386B2

公开(公告)日：2010-05-04

申请号：US12141045

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/44

CPC分类号： H01L21/0228 ,  C23C16/45529 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/11563

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

摘要翻译： 提供了一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的介电层。

公开(公告)号：US20070076477A1

公开(公告)日：2007-04-05

申请号：US11243771

申请日：2005-10-05

申请人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

发明人： Jiunn-Ren Hwang ,  Min-Hwa Chi ,  Fu-Liang Yang

IPC分类号： G11C14/00

CPC分类号： G11C16/0475 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42348 ,  H01L29/785 ,  H01L29/7923

摘要： A 2-bit FinFET flash memory cell capable of storing 2 bits and a method of forming the same are provided. The memory cell includes a semiconductor fin on a top surface of a substrate, a gate insulation film on the top surface and sidewalls of a channel section of the semiconductor fin, a gate electrode on the gate insulation film, and two charge-trapping regions along opposite sides of the gate electrode, wherein each charge-trapping region is separated from the gate electrode and the semiconductor fin by a tunneling layer. The memory cell further includes a protective layer on the charge-trapping regions. Each of the two charge-trapping regions is capable of storing one bit. The memory cell can be operated by applying different bias voltages to the source, the drain, and the gate of the memory cell.

摘要翻译： 提供能够存储2位的2位FinFET闪存单元及其形成方法。 存储单元包括在衬底的顶表面上的半导体鳍片，顶表面上的栅极绝缘膜和半导体鳍片的沟道部分的侧壁，栅极绝缘膜上的栅电极和沿着两个电荷捕获区域 栅电极的相对侧，其中每个电荷俘获区域通过隧道层与栅极电极和半导体鳍片分离。 存储单元还包括在电荷捕获区上的保护层。 两个电荷捕获区域中的每一个能够存储一个位。 可以通过向存储器单元的源极，漏极和栅极施加不同的偏置电压来操作存储器单元。

公开(公告)号：US20060091490A1

公开(公告)日：2006-05-04

申请号：US11077478

申请日：2005-03-10

申请人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

发明人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC分类号： H01L31/105

CPC分类号： H01L29/7391 ,  H01L29/868

摘要： A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and the gate electrode; a source doped with a first type of dopant substantially under the source gate spacer wherein the source has a horizontal distance from a first edge of the gate electrode; a drain doped with the opposite type of the source substantially under the drain spacer and substantially aligned horizontally with a second edge of the gate electrode; a source silicide adjacent the source; and a drain silicide adjacent the drain.

摘要翻译： 门式p-i-n二极管及其形成方法。 门控p-i-n二极管包括：半导体衬底; 半导体衬底上的栅极电介质; 栅电极上的栅电极; 源栅极间隔物和漏极栅极间隔物，沿着栅极电介质和栅电极的相应边缘; 源极掺杂有基本上在源栅极间隔物下方的第一类型掺杂剂的源，其中源极与栅电极的第一边缘具有水平距离; 基本上在所述漏极间隔物的下方掺杂有相反类型的源极的漏极，并且与所述栅极电极的第二边缘基本对准; 邻近源极的源硅化物; 和漏极附近的漏极硅化物。

公开(公告)号：US20050212083A1

公开(公告)日：2005-09-29

申请号：US11102340

申请日：2005-04-08

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L27/08 ,  H01L29/772 ,  H01L29/808 ,  H01L29/8605 ,  H01L29/00

CPC分类号： H01L27/0802 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8605

摘要： A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.

摘要翻译： 一个垂直电阻。 衬底包括由隔离层填充的沟槽。 第一掺杂型区域和第二掺杂型区域形成在沟槽的两侧。 第一掺杂型区域接收控制偏压，第二掺杂型区域接收参考偏置，并且响应于控制偏压和参考电压之间的电压差来调整第二掺杂型区域和衬底之间的电阻 偏压。