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公开(公告)号：US20090319707A1
公开(公告)日：2009-12-24
申请号：US12213470
申请日：2008-06-19
申请人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
发明人： Christopher William Laycock , Antony John Harris , Bruce James Mathewson , Richard Roy Grisenthwaite , Stuart David Biles
IPC分类号： G06F13/40
CPC分类号： G06F13/4221
摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.
摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。
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公开(公告)号：US07401210B2
公开(公告)日：2008-07-15
申请号：US11092984
申请日：2005-03-30
IPC分类号： G06F9/00
CPC分类号： G06F9/3016 , G06F9/30054 , G06F9/322 , G06F9/4486
摘要： Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.
摘要翻译： 在执行子程序之后，执行具有作为其输入操作数的地址的返回指令。 将该输入操作数与一个或多个预定值进行比较以检测匹配，并且根据是否检测到匹配来选择返回指令响应。 因此，返回地址值可以用于调用不同的返回指令响应，例如异常返回响应或过程返回响应。 可以方便地将一个或多个预定地址分配给存储器映射内的最高存储器地址。
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公开(公告)号：US20080046762A1
公开(公告)日：2008-02-21
申请号：US11889644
申请日：2007-08-15
IPC分类号： G06F12/14
摘要： A data processing apparatus and method for protecting system control registers is provided. Processing logic is providing for executing software routines and a plurality of system control registers are used to store access control information for a plurality of system resources available to the processing logic when executing at least some of those software routines. Additionally, at least one write control register is provided, with each field of that register being associated with one or more of the system control registers. Disable control logic is used to generate a disable signal, and when that disable signal is clear access control information can be written into the system control registers, and write restriction data can be written into each of the fields of the at least one write control register. Then, when the disable control logic sets the disable signal, the at least one write control register becomes read only, and for each field that has write restriction data therein those associated system control registers indicated by the write restriction data also become read only. This mechanism provides a very flexible approach for programming which system control registers are to be treated as read only registers.
摘要翻译： 提供一种用于保护系统控制寄存器的数据处理装置和方法。 处理逻辑正在提供执行软件程序，并且当执行这些软件程序中的至少一些时，多个系统控制寄存器用于存储可用于处理逻辑的多个系统资源的访问控制信息。 此外，提供至少一个写入控制寄存器，该寄存器的每个字段与一个或多个系统控制寄存器相关联。 禁止控制逻辑用于产生禁用信号，当禁用信号清除时，访问控制信息可以写入系统控制寄存器，写入限制数据可写入至少一个写入控制寄存器的每个字段 。 然后，当禁用控制逻辑设置禁止信号时，至少一个写入控制寄存器变为只读，并且对于其中具有写入限制数据的每个字段，由写入限制数据指示的那些相关联的系统控制寄存器也变为只读。 这种机制提供了非常灵活的编程方式，哪些系统控制寄存器被视为只读寄存器。
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14.发明申请公开(公告)号：US20070294592A1
公开(公告)日：2007-12-20
申请号：US11442593
申请日：2006-05-30
申请人： Edmond John Simon Ashfield , Michael John Williams , John Michael Horley , Richard Roy Grisenthwaite
发明人： Edmond John Simon Ashfield , Michael John Williams , John Michael Horley , Richard Roy Grisenthwaite
IPC分类号： G06F11/00
CPC分类号： G06F9/3804 , G06F9/3844 , G06F11/3447 , G06F11/3471 , G06F11/348 , G06F11/3636 , G06F2201/88 , Y02D10/34
摘要： Tracing logic for monitoring a stream of processing instructions from a program being processed by a data processor is disclosed, said tracing logic comprising monitoring logic operable to detect processing of said instructions in said instruction stream; detect which of said instructions in said instruction stream are conditional direct branch instructions, which of said instructions in said instruction stream are conditional indirect branch instructions and which of said instructions in said instruction stream are unconditional indirect branch instructions; said tracing logic further comprising compression logic operable to: designate said conditional direct branch instructions, said conditional indirect branch instructions and said indirect branch instructions as marker instructions; for each marker instruction, output an execution indicator indicating if said marker instruction has executed or a non-execution indicator indicating if said marker instruction has not executed and not output data relating to previously processed instructions that are not marker instructions.
摘要翻译： 公开了一种用于从由数据处理器处理的程序监视处理指令流的跟踪逻辑，所述跟踪逻辑包括可操作以检测所述指令流中的所述指令的处理的监视逻辑; 检测所述指令流中的哪个指令是条件直接分支指令，所述指令流中的哪个指令是条件间接分支指令，以及所述指令流中的所述指令中的哪一个是无条件间接分支指令; 所述跟踪逻辑还包括压缩逻辑，可操作用于：将所述条件直接分支指令，所述条件间接分支指令和所述间接分支指令指定为标记指令; 对于每个标记指令，输出指示所述标记指令是否已经执行的执行指示符或者指示是否所述标记指令未被执行的非执行指示符，而不输出与先前处理过的指令不是标记指令有关的数据。
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公开(公告)号：US07206884B2
公开(公告)日：2007-04-17
申请号：US10775334
申请日：2004-02-11
IPC分类号： G06F13/26
CPC分类号： G06F9/4818
摘要： A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.
摘要翻译： 具有嵌套中断控制器24的数据处理系统2支持嵌套的活动中断。 与系统正在运行时，与不同中断关联的优先级别是可改变的（可能是可编程的）。 为了防止在嵌套中断中与优先级颠倒相关的问题，嵌套中断控制器在考虑暂挂中断是否应该预先占用现有的活动中断时，将待处理中断的优先级与任何当前活动中断的最高优先级进行比较， 嵌套在一起
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公开(公告)号：US06851033B2
公开(公告)日：2005-02-01
申请号：US10260545
申请日：2002-10-01
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3867 , G06F12/0215
摘要： The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An earlier indication can be provided that at least two memory accesses may be required to access a data item by performing a prediction based upon one or more operands generated from a memory instruction instead of waiting for a memory access generation stage to generate the memory access. Prediction logic can generate a prediction signal to prevent the memory access generation stage from receiving signals from a preceding pipeline stage while at least two memory accesses are being generated.
摘要翻译： 本发明涉及用于预测数据处理装置中的存储器访问的技术，特别涉及用于确定要访问的数据项是否跨越地址边界并将因此需要多个存储器访问的技术。 可以提供先前的指示，可能需要至少两个存储器访问以通过基于从存储器指令生成的一个或多个操作数执行预测而不是等待存储器访问生成阶段来生成存储器访问来访问数据项。 预测逻辑可以产生预测信号，以防止存储器访问生成阶段在生成至少两个存储器访问期间接收来自前一流水线级的信号。
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公开(公告)号：US09569365B2
公开(公告)日：2017-02-14
申请号：US14113723
申请日：2012-05-21
IPC分类号： G06F12/0875 , G06F12/08 , G06F9/38 , G06F9/30
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/3834 , G06F12/0815 , G06F12/0817
摘要： A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.
摘要翻译： 数据处理系统包括多个交易主机，每个具有相关联的本地高速缓冲存储器并且耦合到相干互连电路。 相干互连电路内的监控电路维护关于每个交易主机的状态变量（标志），以监视该交易主机的独占存储访问状态是否正在等待。 当事务主机要执行存储专用指令时，将该事务主机的主体状态变量的当前值与设置独占存储访问时存储的该变量的先前值进行比较。 如果存在匹配，则允许存储专用指令继续进行，并且具有挂起的独占存储访问状态的所有其他事务主器件的状态变量被改变。 如果没有匹配，则专用指令的执行被标记为失败。
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18.发明授权公开(公告)号：US09355014B2
公开(公告)日：2016-05-31
申请号：US13137375
申请日：2011-08-10
IPC分类号： G06F9/318 , G06F11/267 , G06F11/36 , G06F9/455 , G06F9/30
CPC分类号： G06F11/3644 , G06F9/3004 , G06F9/30112 , G06F9/30149 , G06F9/30189 , G06F9/45554 , G06F11/3648
摘要： A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.
摘要翻译： 提供了包括数据处理电路和调试电路的数据处理装置。 当在调试模式下操作时，调试电路控制处理电路的操作。 数据处理电路在进入调试模式时确定数据处理装置的当前操作状态。 数据处理电路根据确定的当前操作状态分配要用作调试指令集的多个指令集中的一个。
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公开(公告)号：US08839038B2
公开(公告)日：2014-09-16
申请号：US13372829
申请日：2012-02-14
CPC分类号： G06F11/2236 , G06F11/3632
摘要： A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.
摘要翻译： 一种用于控制处理器以单步模式执行使得来自指令流的单个指令被执行的方法和装置，处理器确定单个指令是否是至少一种预定类型的指令中的一种，并将类型指示器存储在 在处理器处理单个指令之后，采集数据存储位置和诊断异常。 此外，执行诊断操作，包括访问存储在数据存储位置中的类型指示符，并且当单个指令不是预定类型中的一个时，控制处理器以单步模式继续执行指令，并且当单个指令 指令是至少一种预定类型之一，控制处理器退出单步模式，并且不执行指令流内的下一条指令作为跟随异常的单个指令。
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20.发明授权Alias management within a virtually indexed and physically tagged cache memory 有权虚拟索引和物理标记的高速缓存内存中的别名管理公开(公告)号：US08417915B2
公开(公告)日：2013-04-09
申请号：US11197523
申请日：2005-08-05
IPC分类号： G06F12/00
CPC分类号： G06F12/1045 , G06F12/0864 , G06F12/1063
摘要： A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.
摘要翻译： 描述了虚拟索引和物理标记的存储器，其具有可以超过最小页表大小的高速缓存路径大小，使得高速缓存路径12内的别名虚拟地址VA可以映射到相同的物理地址PA。 混叠管理逻辑10允许来自相同物理地址的数据的多个副本被存储在给定或不同的高速缓存方式内的高速缓存内的不同虚拟索引处。
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