公开(公告)号：US06536249B2

公开(公告)日：2003-03-25

申请号：US10134527

申请日：2002-04-30

Applicant: Wen-Bin Wu

Inventor： Wen-Bin Wu

IPC: E05B1310

CPC classification number: E05B13/108 ,  E05B2063/207 ,  Y10T70/5394 ,  Y10T70/5504 ,  Y10T70/5792 ,  Y10T70/5832

Abstract: A lock device that may be locked automatically includes a base fixed on a door plate. An actuating tube received in the hole of the base is provided with a locking member combined with a handle. The lock core unit has a lock core that may drive an actuating plate to rotate. The drive wheel has a drive slot for insertion of the actuating plate, so that the drive wheel and the actuating plate may be rotated simultaneously. An elastic member has two stop ends rested on the leg of the restoring wheel, and rested on the two sides of the ear plate of the locking plate. The drive plate has a first end inserted into an unlocking rotation knob of the other side of the door plate, and a second end inserted into the drive slot of the drive wheel.

公开(公告)号：US08399891B2

公开(公告)日：2013-03-19

申请号：US12943933

申请日：2010-11-11

Applicant: Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

Inventor： Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

IPC: H01L29/72

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 在衬底上形成包括分离的扫描线图案的第一图案化导电层。 每个扫描线图案包括彼此相邻的第一和第二扫描线。 第一和第二扫描线都具有第一和第二触点。 执行对扫描线图案的公开检查。 沟道层形成在衬底上。 包括与第一和第二扫描线隔开的数据线，位于沟道层上方的源极和漏极以及连接器的第二图案化导电层形成在衬底上。 电源相应地电连接数据线。 至少一个连接器电连接第一和第二扫描线，以便在每个扫描线图案中形成环。 形成与漏极电连接的像素电极。

公开(公告)号：US20120043558A1

公开(公告)日：2012-02-23

申请号：US12943933

申请日：2010-11-11

Applicant: Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

Inventor： Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

IPC: H01L27/15 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 在衬底上形成包括分离的扫描线图案的第一图案化导电层。 每个扫描线图案包括彼此相邻的第一和第二扫描线。 第一和第二扫描线都具有第一和第二触点。 执行对扫描线图案的公开检查。 沟道层形成在衬底上。 包括与第一和第二扫描线隔开的数据线，位于沟道层上方的源极和漏极以及连接器的第二图案化导电层形成在衬底上。 电源相应地电连接数据线。 至少一个连接器电连接第一和第二扫描线，以便在每个扫描线图案中形成环。 形成与漏极电连接的像素电极。

公开(公告)号：US20080251933A1

公开(公告)日：2008-10-16

申请号：US11845746

申请日：2007-08-27

Applicant: Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Chia-Cheng Lin

Inventor： Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Chia-Cheng Lin

IPC: H01L23/525 ,  H01L23/52

CPC classification number: H01L23/528 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.

Abstract translation: 金属互连结构包括彼此相邻的多个第一插塞，第一金属线在第一方向上延伸并接触每个第一插塞以形成第一部分，第一部分之间具有锥形第二部分，第二插头与第二插头相邻 在第一方向垂直的第二方向上。

公开(公告)号：US07304323B2

公开(公告)日：2007-12-04

申请号：US10732370

申请日：2003-12-11

Applicant: Wen-Bin Wu

Inventor： Wen-Bin Wu

IPC: H01L23/58 ,  H01L29/10

CPC classification number: H01L22/12 ,  G03F1/44 ,  G03F7/70625

Abstract: Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second pattern density. In the test mask structure of the present invention, the required pattern density is obtained by adjusting the area of the array pattern region and the area of the test mask pattern region according to the first pattern density and the second pattern density.

Abstract translation: 公开了一种测试掩模结构。 本发明的测试掩模结构至少包括与最终产品一定比例的阵列图案区域，其具有按照一定比例的第一图案密度; 以及具有第二图案密度的至少一个测试掩模图案区域。 在本发明的测试掩模结构中，通过根据第一图案密度和第二图案密度调整阵列图案区域的面积和测试掩模图案区域的面积来获得所需的图案密度。

公开(公告)号：US06929902B2

公开(公告)日：2005-08-16

申请号：US10370441

申请日：2003-02-20

Applicant: Yuan-Hsun Wu ,  Teng-Yen Huang ,  Wen-Bin Wu ,  Yi-Nan Chen

Inventor： Yuan-Hsun Wu ,  Teng-Yen Huang ,  Wen-Bin Wu ,  Yi-Nan Chen

IPC: G03F7/42 ,  H01L21/027 ,  H01L21/311 ,  G03F7/36

CPC classification number: G03F7/427 ,  H01L21/0276 ,  H01L21/31138

Abstract: A method of preventing repeated collapse in a reworked photoresist layer. First, oxygen-containing plasma is applied to remove a collapsed photoresist. Because the plasma containing oxygen reacts with a bottom anti-reflect layer comprising SiOxNy, some acids are produced on the bottom anti-reflect layer, resulting in undercutting in a subsequently reworked photoresist. Next, an alkaline solution treatment is performed on the anti-reflect layer after the collapsed photoresist layer is removed. Finally, the reworked photoresist with is formed on the anti-reflect layer, without undercutting.

Abstract translation: 防止再加工的光致抗蚀剂层中的重复塌陷的方法。 首先，施加含氧等离子体以除去塌陷的光致抗蚀剂。 因为含有氧的等离子体与包含SiO x N y Y y的底部防反射层反应，所以在底部防反射层上产生一些酸，导致在 随后再加工光致抗蚀剂。 接下来，在去除塌陷的光致抗蚀剂层之后，在抗反射层上进行碱性溶液处理。 最后，在反射层上形成返工光致抗蚀剂，而没有底切。

公开(公告)号：US08658051B2

公开(公告)日：2014-02-25

申请号：US12119275

申请日：2008-05-12

Applicant: Kuo-Yao Cho ,  Wen-Bin Wu ,  Ya-Chih Wang ,  Chiang-Lin Shih ,  Chao-Wen Lay ,  Chih-Huang Wu

Inventor： Kuo-Yao Cho ,  Wen-Bin Wu ,  Ya-Chih Wang ,  Chiang-Lin Shih ,  Chao-Wen Lay ,  Chih-Huang Wu

IPC: C23F1/00 ,  B44C1/22 ,  H01L21/306

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract translation: 一种改善半导体上的光刻分辨率的方法，包括提供其上依次形成保护层，第一蚀刻层和光致抗蚀剂层的基板的步骤; 图案化光致抗蚀剂层以形成开口，以便部分地露出第一蚀刻层; 将第一离子注入到所揭示的第一蚀刻层中以形成第一掺杂区域; 以及将第二离子注入到所揭示的第一蚀刻层中以形成第二掺杂区域，其中所述第一掺杂区域与所述第二掺杂区域无关。

公开(公告)号：US07090965B2

公开(公告)日：2006-08-15

申请号：US10611196

申请日：2003-07-01

Applicant: Wen-Bin Wu ,  Yuan-Shan Wu ,  Yi-Nan Chen ,  Teng-Yen Huang

Inventor： Wen-Bin Wu ,  Yuan-Shan Wu ,  Yi-Nan Chen ,  Teng-Yen Huang

IPC: G03F7/00

CPC classification number: H01L21/0276 ,  G03F7/085 ,  G03F7/11

Abstract: A method for enhancing adhesion between a reworked photoresist and an underlying oxynitride film. A photoresist pattern layer is formed on an oxynitride layer overlying a substrate. The photoresist pattern layer is removed by acidic solution or oxygen-containing plasma. A surface treatment is performed on the oxynitride layer using a development solution to repair the damaged oxynitride layer due to removing the overlying photoresist pattern layer. A reworked photoresist pattern layer is formed on the oxynitride layer.

Abstract translation: 一种用于增强再加工的光致抗蚀剂和潜在的氮氧化合物膜之间的粘合性的方法。 在衬底上的氧氮化物层上形成光致抗蚀剂图案层。 通过酸性溶液或含氧等离子体去除光致抗蚀剂图案层。 使用显影液在氧氮化物层上进行表面处理，以通过除去上覆的光致抗蚀剂图案层来修复损坏的氮氧化物层。 在氧氮化物层上形成再加工的光致抗蚀剂图案层。

公开(公告)号：US20050168740A1

公开(公告)日：2005-08-04

申请号：US11090643

申请日：2005-03-25

Applicant: Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

Inventor： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

IPC: G03F7/20 ,  G03F9/00 ,  G01B11/00 ,  G06F17/50

CPC classification number: G03F9/7019 ,  G03F7/70633 ,  G03F9/7011

Abstract: A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

Abstract translation: 一种用于评估两个掩模版图案之间的掩模版配准的方法。 通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。 在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。 通过CD-SEM测量第一和第二曝光图案之间的偏差值。 根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。 基于登记数据评价两个掩模图案之间的掩模版登记。

公开(公告)号：US20050022150A1

公开(公告)日：2005-01-27

申请号：US10707244

申请日：2003-12-01

Applicant: Shu-Hui Liu ,  Wen-Bin Wu

Inventor： Shu-Hui Liu ,  Wen-Bin Wu

IPC: G03C5/00 ,  G03F1/00 ,  G03F1/36 ,  G03F7/20 ,  G03F9/00 ,  G06F17/50

CPC classification number: G03F1/36

Abstract: An optical proximity correction (OPC) method for correcting a photomask layout. The photomask layout has at least a photomask pattern. The steps of the OPC method include collecting an assist feature bias of a predetermined assist feature, performing a rule-based OPC by taking account of the assist feature bias to compute a target bias of the photomask layout, outputting a corrected photomask layout according to the target bias, and adding the predetermined assist feature to the corrected photomask layout.

Abstract translation: 一种用于校正光掩模布局的光学邻近校正（OPC）方法。 光掩模布局至少具有光掩模图案。 OPC方法的步骤包括收集预定辅助特征的辅助特征偏差，通过考虑辅助特征偏差来执行基于规则的OPC，以计算光掩模布局的目标偏置，根据该方法输出校正的光掩模布局 目标偏置，并将预定的辅助特征添加到校正的光掩模布局。