公开(公告)号：US6137132A

公开(公告)日：2000-10-24

申请号：US109348

申请日：1998-06-30

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The structure of flash EEPROM is formed on a composite substrate, wherein said composite substrate comprises: a pad oxide layer formed on a semiconductor substrate; an n-type doped dielectric layer is formed on the pad oxide layer. A nitride layer is formed on the n-type doped oxide layer. The composite substrate has a trench. An oxynitride layer which serves as coupling oxide layer is formed on surfaces of sidewalls and bottom of portion of the semiconductor substrate of the trench. The trench is filled with an n-type conductive doped polysilicon layer. The n-type conductive doped polysilicon layer serves as a floating gate of EEPROM. A conductive layer, a semiconductor substrate layer doped by using aforementioned n-type dopant containing oxide as a diffusion source, serves as buried bit lines being formed in the semiconductor substrate and abutting the pad oxide layer. An ONO layer is formed on the polysilicon layer and the nitride layer. Finally, another n+ conductive layer is formed on the ONO layer as word line.

Abstract translation: 闪存EEPROM的结构形成在复合衬底上，其中所述复合衬底包括：形成在半导体衬底上的衬垫氧化层; 在衬垫氧化物层上形成n型掺杂介质层。 在n型掺杂氧化物层上形成氮化物层。 复合衬底具有沟槽。 在沟槽的半导体衬底的部分的侧壁和底部的表面上形成用作耦合氧化物层的氧氮化物层。 沟槽填充有n型导电掺杂多晶硅层。 n型导电掺杂多晶硅层用作EEPROM的浮动栅极。 通过使用上述含有n型掺杂剂的氧化物作为扩散源掺杂的导电层，半导体衬底层用作在半导体衬底中形成并与衬垫氧化物层邻接的掩埋位线。 在多晶硅层和氮化物层上形成ONO层。 最后，在ONO层上形成另一个n +导电层作为字线。

公开(公告)号：US6130135A

公开(公告)日：2000-10-10

申请号：US81396

申请日：1998-05-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/6659 ,  H01L21/28114 ,  H01L29/6656 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/42376

Abstract: A method of fabricating a lightly doped drain transistor having an inverse-T gate structure. A semiconductor substrate is provided to implement said method. After a gate dielectric layer is formed on the substrate, the step of sequentially forming a first amorphous silicon layer and a second amorphous silicon layer follows. Then, the second amorphous silicon layer is patterned to form a first electrode, and first spacers are formed on sidewalls of the first electrode. Lightly-doped layers are thereafter formed in the substrate, and thus the first amorphous silicon layer is patterned to form a second electrode. Both steps make use of the first electrode and the first spacers as masking. Subsequently, second spacers are formed to overlie the first spacers and sidewalls of the second electrode. After heavily-doped layers are formed in the substrate by using the first electrode and the second spacers as masking, the lightly-doped layers are driven in so as to be fully covered by the second electrode.

Abstract translation: 一种制造具有逆T栅极结构的轻掺杂漏极晶体管的方法。 提供半导体衬底以实现所述方法。 在基板上形成栅介质层之后，依次形成第一非晶硅层和第二非晶硅层。 然后，对第二非晶硅层进行构图以形成第一电极，并且在第一电极的侧壁上形成第一间隔物。 此后在衬底中形成轻掺杂层，因此第一非晶硅层被图案化以形成第二电极。 两个步骤都利用第一电​​极和第一间隔物作为掩蔽。 随后，形成第二间隔物以覆盖第一间隔物和第二电极的侧壁。 在通过使用第一电极和第二间隔物作为掩模在衬底中形成重掺杂层之后，轻掺杂层被驱动以被第二电极完全覆盖。

公开(公告)号：US6117756A

公开(公告)日：2000-09-12

申请号：US336869

申请日：1999-06-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/02 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L28/82 ,  H01L29/66825

Abstract: The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed thereupon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed thereover. A portion of the first nitride layer and a portion of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and to drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and a first conductive layer is then formed over the substrate. A doping process is performed to dope the pad oxide layer, the first oxide layer, and the second oxide layer by implanting second type dopants through the first conductive layer. A second thermal process is performed and a portion of the first conductive layer is removed to define a floating gate. A dielectric layer is formed over the semiconductor substrate and a second conductive layer is then formed thereover as a control gate.

Abstract translation: 用于形成闪速存储器的方法包括以下步骤。 首先，提供其上形成有隔离区域的半导体衬底。 半导体衬底具有衬垫氧化物层和在其上形成的第一氮化物层。 第一氮化物层的一部分和衬垫氧化物层的一部分被去除以限定栅极区域。 形成第一氧化物层，然后形成侧壁结构。 半导体衬底掺杂有第一类型掺杂剂。 执行第一热处理以形成第二氧化物层并驱动第一类型掺杂剂。 然后去除侧壁结构和第一氮化物层，然后在衬底上形成第一导电层。 通过将第二类型掺杂剂注入第一导电层，进行掺杂工艺以掺杂衬垫氧化物层，第一氧化物层和第二氧化物层。 执行第二热处理，并且去除第一导电层的一部分以限定浮动栅极。 在半导体衬底上形成介电层，然后在其上形成第二导电层作为控制栅极。

公开(公告)号：US6117712A

公开(公告)日：2000-09-12

申请号：US248955

申请日：1999-02-12

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/78654 ,  H01L29/66613 ,  H01L29/66772 ,  H01L29/78696 ,  H01L29/665

Abstract: The method includes forming a buried oxide layer in a substrate. A pad oxide layer is then formed on the substrate. A silicon nitride layer is pattered on the surface of the pad oxide. Then, a thick field oxide (FOX) is formed on the pad oxide layer. Sidewall spacers are formed on the side walls of the opening of the silicon nitride layer. Next, the FOX is etched. An ion implantation is performed for adjusting the threshold voltage and anti-punch-through implantation. Subsequently, a dielectric with high permittivity is deposited along the surface of the substrate. The dielectric layer may be formed by a nitride technique. A conductive layer composed of metal or alloy is then formed on the dielectric layer and refilled into the opening. A chemical mechanical polishing is used to remove the dielectric layer, silicon nitride and the spacers such that the conductive layer remains only in the opening. The residual nitride and spacers are removed by hot phosphor acid solution. Source and drain are next created. The pad oxide layer and the FOX are then removed. Then, the lightly doped drain (LDD) are formed. A self-aligned silicide (SALICIDE) layer is formed on the substrate exposed by the gate.

Abstract translation: 该方法包括在衬底中形成掩埋氧化物层。 然后在衬底上形成衬垫氧化物层。 氮化硅层在衬垫氧化物的表面上图案化。 然后，在衬垫氧化物层上形成厚场氧化物（FOX）。 侧壁间隔物形成在氮化硅层的开口的侧壁上。 接下来，FOX被蚀刻。 执行离子注入以调整阈值电压和抗穿透植入。 随后沿着衬底的表面沉积具有高介电常数的电介质。 电介质层可以通过氮化物技术形成。 然后在介电层上形成由金属或合金构成的导电层，并重新填充到开口中。 使用化学机械抛光来去除介电层，氮化硅和间隔物，使得导电层仅保留在开口中。 通过热磷酸溶液除去残留的氮化物和间隔物。 源和漏是下一个创建的。 然后去除垫氧化物层和FOX。 然后，形成轻掺杂漏极（LDD）。 在由栅极暴露的衬底上形成自对准硅化物（SALICIDE）层。

公开(公告)号：US6107126A

公开(公告)日：2000-08-22

申请号：US13425

申请日：1998-01-26

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246

CPC classification number: H01L27/11293

Abstract: A method for fabricating a Read Only Memory, (ROM), cell on a semiconductor substrate with device region and programmable cell region. The method includes the followed step. A plurality of field oxide regions is formed on the semiconductor substrate. A P-well and an N-well are formed in the device region of the semiconductor substrate, a P-well is formed in the programmable cell region of the substrate. A photoresist is formed over the N-well in the device region. Next, a phosphorus ion implantation is performed into the P-well in the device region for anti-punchthrough and into the N-well in the programmable region to form buried channel by using the photoresist layer as implant mask. After removing the photoresisit, a CMOS transistor is formed on the device region, and a NMOS transistor is formed on the programmable cell region.

Abstract translation: 一种制造只读存储器（ROM）的方法，在具有器件区域和可编程单元区域的半导体衬底上形成单元。 该方法包括随后的步骤。 在半导体衬底上形成多个场氧化物区域。 在半导体衬底的器件区域中形成P阱和N阱，在衬底的可编程单元区域中形成P阱。 在器件区域中的N阱上形成光致抗蚀剂。 接下来，在用于防穿透的装置区域中的P阱中进行磷离子注入，并且通过使用光致抗蚀剂层作为植入掩模来进入可编程区域中的N阱中以形成掩埋沟道。 在去除光电传感器之后，在器件区域上形成CMOS晶体管，并且在可编程单元区域上形成NMOS晶体管。

公开(公告)号：US6096614A

公开(公告)日：2000-08-01

申请号：US20229

申请日：1998-02-06

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/336

CPC classification number: H01L21/28194 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/518

Abstract: The method of the present invention is a method to fabricate a MOS device without boron penetration. After growing a gate oxide layer, a thin stacked-amorphous-silicon layer (SAS) is deposited over the oxide layer. Subsequently, a lightly nitrogen ion is implanted into the stacked-amorphous silicon layer. The stacked-amorphous silicon layer is patterned to define a gate structure. Then, a light doped ion implantation is performed to dope ions through the gate oxide layer into the substrate to form lightly doped source and drain regions. A dielectric layer is formed over the gate structure and the gate oxide layer, and the dielectric layer is etched to form sidewall spacers. Next, a second ion implantation is performed to dope ions into the substrate to form source and drain. Finally, a thermal annealing is performed on the stacked-amorphous silicon gate and the substrate. The nitrogen ions in the stacked-amorphous silicon gate are segregated into the gate oxide layer to act as a diffusive barrier, the stacked-amorphous silicon gate being convert into ploy silicon gate and thereby forming shallow source and drain junction in the substrate.

Abstract translation: 本发明的方法是制造没有硼渗透的MOS器件的方法。 在生长栅极氧化物层之后，在氧化物层上沉积薄的堆叠非晶硅层（SAS）。 随后，将轻微的氮离子注入到堆积的非晶硅层中。 将堆叠的非晶硅层图案化以限定栅极结构。 然后，进行轻掺杂离子注入以将离子通过栅极氧化物层掺入衬底中以形成轻掺杂的源极和漏极区域。 在栅极结构和栅极氧化物层之上形成介电层，并且蚀刻电介质层以形成侧壁间隔物。 接下来，进行第二离子注入以将离子掺杂到衬底中以形成源极和漏极。 最后，对堆叠的非晶硅栅极和衬底进行热退火。 层叠的非晶硅栅极中的氮离子被分离到栅极氧化物层中作为扩散势垒，堆积的非晶硅栅极被转换为硅硅栅极，从而在衬底中形成浅的源极和漏极结。

公开(公告)号：US6091119A

公开(公告)日：2000-07-18

申请号：US113931

申请日：1998-07-10

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/11266 ,  H01L27/112 ,  H01L27/11246 ,  H01L27/1126

Abstract: The mask ROM cell structure is described as follows: a plurality of first polysilicon gates is formed on the semiconductor substrate, being separated to keep a space. Each of first polysilicon gates comprises first nitride layer/ a n+ polysilicon layer/a first pad oxide layer, and two spacers that formed over the remnant portion of the pad oxide layer, and formed, respectively, on two sidewalls of the first nitride layer 130, and the first n+ polysilicon layer. A plurality of second polysilicon gates is formed on the semiconductor substrate 105. Each of the second polysilicon gates comprises second n+doped polysilicon gate/second pad oxide layer, wherein the pad oxide layer is formed on the semiconductor substrate, and the n+doped polysilicon gate is formed on the second pad oxide layer. The first polysilicon gates separate the second polysilicon gates each.

Abstract translation: 掩模ROM单元结构描述如下：在半导体衬底上形成多个第一多晶硅栅极，被分离以保持空间。 每个第一多晶硅栅极包括第一氮化物层/ n +多晶硅层/第一焊盘氧化物层，以及形成在焊盘氧化物层的残余部分上并分别形成在第一氮化物层130的两个侧壁上的两个间隔物 和第一n +多晶硅层。 在半导体衬底105上形成多个第二多晶硅栅极。每个第二多晶硅栅极包括第二n +掺杂多晶硅栅极/第二焊盘氧化物层，其中衬底氧化物层形成在半导体衬底上，并且n +掺杂 多晶硅栅极形成在第二焊盘氧化物层上。 第一多晶硅栅极分开第二多晶硅栅极。

公开(公告)号：US6090653A

公开(公告)日：2000-07-18

申请号：US243916

申请日：1999-02-03

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8238

CPC classification number: H01L21/823835

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a tilted angle relative to the normal line of the substrate is used. The tilted angle is about 30 to 90 degrees respect to the substrate. The ions pass through the spacers, gate oxide and into the substrate under a portion of the gate by controlling the energy of the ion implantation. The spacers also doped with ions during the implantation. The energy of the ion implantation is about 5 to 150 KeV, and the dosage of the ion implantation is about 5E12 to 2E15 atoms/cm.sup.2. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitrogen doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form a shallow source and drain junction.

Abstract translation: 本发明包括在基板上形成具有氮化物盖的栅极结构。 离子注入用于将离子掺杂到衬底中以形成轻掺杂漏极（LDD）结构。 在栅极结构上形成氧化物层。 随后，氧化层被回蚀刻以在栅极结构的侧壁上形成氧化物间隔物。 接下来，使用相对于基板的法线具有倾斜角的离子注入。 倾斜角相对于基底约30度至90度。 通过控制离子注入的能量，离子通过间隔物，栅极氧化物并通过栅极的一部分进入衬底。 间隔物在植入期间也掺杂有离子。 离子注入的能量约为5至150KeV，离子注入的用量约为5E12至2E15原子/ cm2。 然后去除盖子氮化硅层。 然后，将耐火或贵金属层溅射在衬底上，掺杂氮的氧化物隔离物和栅极。 进行第一步热处理以形成杀真菌剂和多杀菌剂。 接下来，使用离子注入来将离子掺入到杀真菌剂和聚酰胺膜中。 采用第二步热处理形成浅源极和漏极结。

公开(公告)号：US06084275A

公开(公告)日：2000-07-04

申请号：US072291

申请日：1998-05-04

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8246 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11253 ,  H01L27/11293

Abstract: The present invention includes a normal NMOS device region and a NMOS cell region for coding. An isolation structure is formed between the normal NMOS device region and the NMOS cell region. A gate oxide is formed on the normal NMOS device region and a coding oxide is formed on the NMOS cell region. A polysilicon layer is formed on the gate oxide. Gates are respectively formed on the polysilicon layer and the coding oxide. Spacers are formed on the side walls of the gates. LDD structures are formed under the spacers and adjacent to the gates. Source and drain regions are formed next to the LDD structures. A p type conductive region is formed adjacent to the surface of the NMOS cell region and under the coding oxide.

Abstract translation: 本发明包括通常的NMOS器件区域和用于编码的NMOS单元区域。 在正常NMOS器件区域和NMOS单元区域之间形成隔离结构。 在正常NMOS器件区上形成栅极氧化物，并在NMOS单元区域上形成编码氧化物。 在栅极氧化物上形成多晶硅层。 栅极分别形成在多晶硅层和编码氧化物上。 隔板形成在门的侧壁上。 LDD结构形成在间隔件之下并且邻近门。 源极和漏极区域形成在LDD结构的旁边。 形成与NMOS单元区域的表面相邻并且在编码氧化物下面的p型导电区域。

公开(公告)号：US06084261A

公开(公告)日：2000-07-04

申请号：US232552

申请日：1999-01-18

Applicant: Shye-Lin Wu

Inventor： Shye-Lin Wu

IPC: H01L21/8242 ,  H01L27/108 ,  H07L27/108

CPC classification number: H01L27/10817 ,  H01L27/10852

Abstract: A fork-shaped capacitor of a dynamic random access memory cell is disclosed. This capacitor includes a semiconductor layer (110), and a first dielectric layer (119) formed over the semiconductor layer. The capacitor also includes a first conductive region (118) formed on a portion of the first dielectric layer, the first conductive region communicating to the semiconductor layer via a hole in the first dielectric layer. At least two second conductive regions (122) are formed on the first conductive region, each of the conductive regions being spaced from each other. Further, at least two third conductive regions (126) are formed on the first dielectric layer, each of the third conductive regions being spaced from each other, each of the third conductive regions being spaced from each of the second conductive regions, wherein a portion of each of the third conductive regions abuts a sidewall of the first conductive region. Finally, the capacitor includes a second dielectric film (136) formed on surface of the first conductive region, the second conductive regions, and the third conductive regions; and a conductive layer (138) formed on the second dielectric film.

Abstract translation: 公开了一种动态随机存取存储器单元的叉形电容器。 该电容器包括半导体层（110）和形成在半导体层上的第一介电层（119）。 电容器还包括形成在第一电介质层的一部分上的第一导电区域（118），第一导电区域经由第一电介质层中的孔与半导体层连通。 至少两个第二导电区域（122）形成在第一导电区域上，每个导电区域彼此间隔开。 此外，至少两个第三导电区域（126）形成在第一介电层上，每个第三导电区域彼此间隔开，每个第三导电区域与每个第二导电区域间隔开，其中一部分 每个第三导电区域邻接第一导电区域的侧壁。 最后，电容器包括形成在第一导电区域，第二导电区域和第三导电区域的表面上的第二电介质膜（136） 和形成在第二电介质膜上的导电层（138）。