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    MASK-SHIFT-AWARE RC EXTRACTION FOR DOUBLE PATTERNING DESIGN
    11.
    发明申请
    MASK-SHIFT-AWARE RC EXTRACTION FOR DOUBLE PATTERNING DESIGN 有权
    MASK-SHIFT-AWARE RC提取双重图案设计

    公开(公告)号：US20120052422A1

    公开(公告)日：2012-03-01

    申请号：US12872938

    申请日：2010-08-31

    Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Hsiao-Shu Chao ,  Ke-Ying Su ,  Cheng-Hung Yeh ,  Dian-Hau Chen ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G03C7/20

    CPC classification number: G03F1/70

    Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

    Abstract translation: 一种方法包括提供集成电路设计的布局，以及从布局生成多个双重图案化分解，多个双重图案化分解中的每一个包括分离到第一掩模的图案和双图案掩模组的第二掩模 。 确定第一和第二掩模之间的最大偏移，其中最大偏移是用于在晶片上实现布局的制造过程中的最大预期掩模移位。 对于多个双重图案化分解中的每一个，使用由最大偏移限定的范围内的掩模移位来模拟最坏情况的性能值。

    Integrated Circuit Design using DFM-Enhanced Architecture
    12.
    发明申请
    Integrated Circuit Design using DFM-Enhanced Architecture 有权
    使用DFM增强架构的集成电路设计

    公开(公告)号：US20100281446A1

    公开(公告)日：2010-11-04

    申请号：US12708242

    申请日：2010-02-18

    Applicant: Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    Inventor： Yung-Chin Hou ,  Lee-Chung Lu ,  Li-Chun Tien ,  Yi-Kan Cheng ,  Chun-Hui Tai ,  Ta-Pen Guo ,  Yuan-Te Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.

    Abstract translation: 集成电路库包括具有第一左边界和第一右边界的第一标准单元，以及具有第二左边界和第二右边界的第二标准单元。 第一标准细胞和第二标准细胞具有相同的细胞变体。 第一标准单元中的第一有源区具有与第二标准单元中的第二有源区不同的扩散长度。 第一有源区和第二有源区是由表示第一标准单元和第二标准单元的相同电路图的相同分量表示的相应有源区。

    Design Methods for E-Beam Direct Write Lithography
    13.
    发明申请
    Design Methods for E-Beam Direct Write Lithography 有权
    电子束直写光刻设计方法

    公开(公告)号：US20100205577A1

    公开(公告)日：2010-08-12

    申请号：US12617470

    申请日：2009-11-12

    Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai

    Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai

    IPC: G06F17/50

    CPC classification number: B82Y40/00 ,  B82Y10/00 ,  G03F1/78 ,  H01J37/3174

    Abstract: A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system.

    Abstract translation: 一种形成用于晶片的集成电路的方法包括提供电子束直接写入（EBDW）系统。 为晶片生成栅格，其中栅格包括栅格线。 为晶片布置了集成电路，其中集成电路中的基本上没有敏感特征跨越电网的栅格线。 使用EBDW系统在晶片上执行EBDW。

    Routing Method for Double Patterning Design
    14.
    发明申请
    Routing Method for Double Patterning Design 有权
    双重图案设计的路由方法

    公开(公告)号：US20100199253A1

    公开(公告)日：2010-08-05

    申请号：US12616956

    申请日：2009-11-12

    Applicant: Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

    Inventor： Yi-Kan Cheng ,  Lee-Chung Lu ,  Ru-Gun Liu ,  Chih-Ming Lai

    IPC: G06F17/50

    CPC classification number: G03F7/70466 ,  G03F1/00 ,  G03F7/70433 ,  G03F7/705 ,  G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of designing a double patterning mask set includes dividing a chip into a grid comprising grid cells; and laying out a metal layer of the chip. In substantially each of the grid cells, all left-boundary patterns of the metal layer are assigned with a first one of a first indicator and a second indicator, and all right-boundary patterns of the metal layer are assigned with a second one of the first indicator and the second indicator. Starting from one of the grid cells in a row, indicator changes are propagated throughout the row. All patterns in the grid cells are transferred to the double patterning mask set, with all patterns assigned with the first indicator transferred to a first mask of the double patterning mask set, and all patterns assigned with the second indicator transferred to a second mask of the double patterning mask set.

    Abstract translation: 一种设计双重图案掩模组的方法包括将芯片划分成包括栅格单元的栅格; 并布置芯片的金属层。 在基本上每个网格单元中，金属层的所有左边界图案被分配有第一指示符和第二指示符中的第一指示符，并且金属层的所有右边界图案被分配有第二指示符 第一指标和第二指标。 从一行中的一个网格单元开始，指示符更改在整行中传播。 将网格单元中的所有图案转移到双重图案掩模组，其中将分配有第一指示符的所有图案转移到双图案掩模组的第一掩模，并且将分配有第二指示符的所有图案转移到第二掩模 双重图案掩模套。

    Methods for Cell Boundary Isolation in Double Patterning Design
    15.
    发明申请
    Methods for Cell Boundary Isolation in Double Patterning Design 有权
    双重图案设计中细胞边界隔离的方法

    公开(公告)号：US20100196803A1

    公开(公告)日：2010-08-05

    申请号：US12616970

    申请日：2009-11-12

    Applicant: Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

    Inventor： Lee-Chung Lu ,  Yi-Kan Cheng ,  Yuan-Te Hou ,  Yung-Chin Hou ,  Li-Chun Tien

    IPC: G03F1/00 ,  G06F17/50

    CPC classification number: G03F1/70 ,  G03F1/00

    Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.

    Abstract translation: 设计用于芯片布局的双重图案掩模组的方法包括设计标准单元。 在每个标准单元中，所有左边界图案被分配有第一指示符和第二指示符中的一个，并且所有右边图案都被分配有第一指示符和第二指示符中的另外一个。 该方法还包括将标准单元放置在芯片布局的一行中。 从行中的一个标准单元开始，标记单元的指示符更改在整行中传播。 具有第一指示符的标准单元中的所有图案被转移到双图案掩模组的第一掩模。 具有第二指示器的标准单元中的所有图案被转移到双重图案掩模组的第二掩模。

    Integrated circuit layout modification
    17.
    发明授权
    Integrated circuit layout modification 有权
    集成电路布局修改

    公开(公告)号：US08856696B2

    公开(公告)日：2014-10-07

    申请号：US13354707

    申请日：2012-01-20

    Applicant: Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

    Inventor： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F17/5077

    Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

    Abstract translation: 公开了改进利用多重图案化技术（MPT）的集成电路（IC）设计的方法。 所述方法包括配置集成电路的第一布局，其具有至少一层具有通过至少两个掩模的制造而形成的特征的层。 该至少一层包括多个活动单元和多个备用单元。 第二布局被配置为重新路由备用单元和活动单元，其中重新路由使用多个备用单元的至少一部分。 比所有至少两个掩模更少，以配置第二个布局。

    COLORING/GROUPING PATTERNS FOR MULTI-PATTERNING
    18.
    发明申请
    COLORING/GROUPING PATTERNS FOR MULTI-PATTERNING 审中-公开
    多种颜色/分组图案

    公开(公告)号：US20130205266A1

    公开(公告)日：2013-08-08

    申请号：US13365546

    申请日：2012-02-03

    Applicant: Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

    Inventor： Wen-Hao Chen ,  Yuan-Te Hou ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F2217/62

    Abstract: A method comprises: accessing a persistent, machine readable storage medium containing data representing an integrated circuit (IC) design to be fabricated using multi-patterning; identifying at least one network of conductive patterns configured to transmit signals that substantially impact timing of at least one circuit in the IC; pre-grouping the at least one network of conductive patterns in a first group; and electronically providing data to an electronic design automation (EDA) tool to cause inclusion in a first single photomask of all portions of the patterns within the first group that are to be formed in a single layer of the IC, wherein the single layer is to be multi-patterned using at least two photomasks.

    Abstract translation: 一种方法包括：访问包含表示将使用多图案化制造的集成电路（IC）设计的数据的持久的机器可读存储介质; 识别被配置为传输基本上影响所述IC中的至少一个电路的定时的信号的导电图案的至少一个网络; 将第一组中的至少一个导电图案网络预分组; 以及将电子数据提供给电子设计自动化（EDA）工具，以使所述第一组中将被形成在所述IC的单个层中的所述图案的所有部分的第一单个光掩模包括在其中，所述单层为 使用至少两个光掩模进行多图案化。

    Methodology for analysis and fixing guidance of pre-coloring layout
    19.
    发明授权
    Methodology for analysis and fixing guidance of pre-coloring layout 有权
    预先着色布局的分析和固定指导方法

    公开(公告)号：US08434043B1

    公开(公告)日：2013-04-30

    申请号：US13480847

    申请日：2012-05-25

    Applicant: Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    Inventor： Chin-Chang Hsu ,  HungLung Lin ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: The present disclosure relates to a method and apparatus for identifying pre-coloring violations and for providing hints and/or warnings to a designer to eliminate the pre-coloring violations. In some embodiments, the method is performed by identifying G0-spaces within a double patterning technology (DPT) layer, of an integrated chip (IC) layout, having a plurality of pre-colored shapes. Violation paths extending between the pre-colored shapes are identified based upon the G0-spaces. Good paths (i.e., paths that will not cause a violation) and bad paths (i.e., paths that will cause a violation) between the pre-colored shapes are also identified. Hints and/or warnings are generated based upon the identified good and bad paths, wherein the hints and/or warnings provide guidance to eliminate the violation paths and develop a violation free IC layout.

    Abstract translation: 本公开涉及一种用于识别预着色违规的方法和装置，并且用于向设计者提供提示和/或警告以消除预着色违规。 在一些实施例中，该方法通过识别具有多个预着色形状的集成芯片（IC）布局的双图案形成技术（DPT）层内的G0空间来执行。 基于G0空格识别在预色图案之间延伸的违规路径。 还识别出良好路径（即，不会引起违规的路径）和不良路径（即将导致违规的路径）。 提示和/或警告是基于所识别的好路径和不良路径生成的，其中提示和/或警告提供指导以消除违规路径并开发无违规IC布局。

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