公开(公告)号：US20200021289A1

公开(公告)日：2020-01-16

申请号：US16582528

申请日：2019-09-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Yongjie CHENG ,  Lei ZHU ,  Kyehyung LEE

IPC: H03K19/00 ,  H03G1/00

Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.

公开(公告)号：US20190260377A1

公开(公告)日：2019-08-22

申请号：US16162960

申请日：2018-10-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Jing BAI ,  Tejasvi DAS ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI

IPC: H03K17/687 ,  H03K17/06 ,  G06F3/01

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

公开(公告)号：US20190115886A1

公开(公告)日：2019-04-18

申请号：US16133045

申请日：2018-09-17

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Alan Mark MORTON ,  Xin ZHAO ,  Lei ZHU ,  Xiaofan FEI ,  Johann G. GABORIAU ,  John L. MELANSON ,  Amar VELLANKI

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00

Abstract: A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

公开(公告)号：US20180212569A1

公开(公告)日：2018-07-26

申请号：US15622722

申请日：2017-06-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Ku HE ,  Xin ZHAO ,  Miao SONG ,  Saurabh SINGH ,  Vinod JAYAKUMAR

IPC: H03F1/02 ,  H03F3/217 ,  H03F3/21 ,  H03F3/183

CPC classification number: H03F1/0205 ,  H03F1/30 ,  H03F1/3264 ,  H03F3/183 ,  H03F3/187 ,  H03F3/21 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2203/45048

Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.