公开(公告)号：US20180212569A1

公开(公告)日：2018-07-26

申请号：US15622722

申请日：2017-06-14

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Lei ZHU ,  Ku HE ,  Xin ZHAO ,  Miao SONG ,  Saurabh SINGH ,  Vinod JAYAKUMAR

IPC: H03F1/02 ,  H03F3/217 ,  H03F3/21 ,  H03F3/183

CPC classification number: H03F1/0205 ,  H03F1/30 ,  H03F1/3264 ,  H03F3/183 ,  H03F3/187 ,  H03F3/21 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2203/45048

Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

公开(公告)号：US20200059200A1

公开(公告)日：2020-02-20

申请号：US16348824

申请日：2018-04-27

Applicant: Graeme Gordon ACKAY ,  Cirrus Logic International Semiconductor Ltd.

Inventor： Graeme Gordon MACKAY ,  Lei ZHU ,  Ku HE ,  Vamsikrishna PARUPALLI

IPC: H03F1/02 ,  H03F3/45 ,  H03F1/30 ,  H03F3/213 ,  H03F3/187

Abstract: In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

公开(公告)号：US20180295442A1

公开(公告)日：2018-10-11

申请号：US15482250

申请日：2017-04-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Xin ZHAO ,  Ku HE ,  Xiaofan FEI

IPC: H04R3/00 ,  H04R29/00 ,  H03F3/185 ,  H03F3/217

CPC classification number: H04R3/00 ,  H03F1/0277 ,  H03F3/185 ,  H03F3/211 ,  H03F3/217 ,  H03F3/2178 ,  H03F3/30 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/411 ,  H03F2200/432 ,  H04R29/00 ,  H04R2420/03

Abstract: In accordance with embodiments of the present disclosure, a system may include a playback path and a control circuit. The playback path may have a playback input for receiving an input signal and configured to generate at a playback path output an output signal based on the input signal, wherein the playback path is configured to operate in a plurality of operational modes. The control circuit may be configured to receive a first signal from within the playback path and indicative of the input signal, receive a second signal generated from the input signal externally to the playback path, and select a selected operational mode from the plurality of operational modes based on the first signal and the second signal.

公开(公告)号：US20190260365A1

公开(公告)日：2019-08-22

申请号：US16144104

申请日：2018-09-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ku HE ,  Tejasvi DAS ,  Xin ZHAO ,  Xiaofan FEI

IPC: H03K7/08 ,  H03G3/00 ,  G05F1/575

Abstract: A method may include, in a system comprising a digital PWM subsystem having a tunable digital gain, a first path coupled to an output of the digital PWM subsystem and configured to drive an open-loop driver stage, and a second path coupled to the output of the digital PWM subsystem and configured to drive a closed-loop driver stage having a tunable analog gain: selecting one of the first path and the second path for processing an input signal to generate an output signal based on one or more characteristics of the input signal, setting the digital gain to a maximum digital gain and the analog gain to a minimum analog gain when the input signal is lesser than a first threshold, setting the digital gain to a minimum digital gain and the analog gain to a maximum analog gain when the input signal is greater than a second threshold magnitude, and varying the analog gain and the digital gain when the input signal is in a range greater than the first threshold and lesser than a second threshold.

公开(公告)号：US20180316313A1

公开(公告)日：2018-11-01

申请号：US15582233

申请日：2017-04-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Graeme Gordon MACKAY ,  Lei ZHU ,  Ku HE ,  Vamsikrishna PARUPALLI

IPC: H03F1/02 ,  H03F3/45

CPC classification number: H03F1/0233 ,  H03F1/0227 ,  H03F1/025 ,  H03F1/30 ,  H03F3/187 ,  H03F3/213 ,  H03F3/45475 ,  H03F3/45973 ,  H03F3/45982 ,  H03F2200/03 ,  H03F2200/375 ,  H03F2200/511 ,  H03F2203/45022 ,  H03F2203/45042 ,  H03F2203/45152 ,  H03F2203/45212 ,  H03F2203/45528 ,  H03F2203/45588 ,  H03F2203/45594 ,  H03F2203/45596 ,  H03F2203/45601 ,  H03F2203/45681

Abstract: In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

公开(公告)号：US20180098149A1

公开(公告)日：2018-04-05

申请号：US15286289

申请日：2016-10-05

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Ku HE ,  John L. MELANSON

IPC: H04R3/04 ,  H03G3/30 ,  H03G3/32 ,  H03F3/187

CPC classification number: H04R3/04 ,  H03F3/187 ,  H03F3/45475 ,  H03F3/45596 ,  H03F2200/78 ,  H03F2203/45048 ,  H03F2203/45522 ,  H03G3/04 ,  H03G3/3005 ,  H03G3/3089 ,  H03G3/32 ,  H03G7/002 ,  H03G7/007 ,  H04R2430/03

Abstract: An analog signal path portion of a signal path may have: (i) an audio input for receiving an analog signal, an audio output for providing an output signal, and a selectable analog gain, and may be configured to generate the output signal based on the analog signal and in conformity with the selectable analog gain; and (ii) a digital path portion having a selectable digital gain and configured to receive a digital input signal and convert the digital input signal into the analog signal in conformity with the selectable digital gain. A control circuit may be configured to modify the digital and analog gains in response to an indication to switch between gain modes of the signal path, determine a noise floor of an audio signal comprising the digital input signal or a signal derived therefrom, and control modification of the digital and analog gains based on the noise floor.