-
公开(公告)号：US20180212569A1
公开(公告)日：2018-07-26
申请号：US15622722
申请日：2017-06-14
Inventor： Lei ZHU , Ku HE , Xin ZHAO , Miao SONG , Saurabh SINGH , Vinod JAYAKUMAR
CPC classification number: H03F1/0205 , H03F1/30 , H03F1/3264 , H03F3/183 , H03F3/187 , H03F3/21 , H03F3/217 , H03F3/2171 , H03F3/45475 , H03F3/45968 , H03F2200/03 , H03F2200/375 , H03F2203/45048
Abstract: A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.
-
公开(公告)号：US20210219396A1
公开(公告)日：2021-07-15
申请号：US17123429
申请日：2020-12-16
Inventor： Dave SMITH , Saurabh SINGH , Andrew BUIST , Paulius CEREBIEJUS , Mark J. MCCLOY-STEVENS , Terence A. ORR
IPC: H05B45/345 , H03F3/04
Abstract: The present disclosure relates to current control circuitry for controlling a current through a load. The current control circuitry comprises amplifier circuitry, reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry and an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; and a current output terminal. The current control circuitry further comprises a variable resistance coupled to the current output terminal of the output stage, and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
-
公开(公告)号：US20210148968A1
公开(公告)日：2021-05-20
申请号：US17065799
申请日：2020-10-08
Inventor： James WELLS , Saurabh SINGH , Huy Binh LE , Gavin WILSON , Niall MCGURNAGHAN , Simon R. FOSTER , Mark MCCLOY-STEVENS
Abstract: The present disclosure relates to self-test circuitry for a system that includes one or more current control subsystems, each current control subsystem having a load terminal for coupling the current control subsystem to a load. The self-test circuitry comprises: a signal path associated with each current control subsystem, each signal path configured to selectively couple a measurement node to the load terminal of the current control subsystem, wherein the measurement node is common to all of the signal paths; voltage detection circuitry; and test voltage source circuitry configured to provide a test voltage to the measurement node. The voltage detection circuitry is operable to output a signal indicative of a fault condition if a voltage detected at the measurement node differs from the test voltage when the measurement node is coupled to the load terminal.
-
公开(公告)号：US20180048325A1
公开(公告)日：2018-02-15
申请号：US15234741
申请日：2016-08-11
Inventor： Edmund Mark SCHNEIDER , Daniel J. ALLEN , Saurabh SINGH , Aniruddha SATOSKAR
CPC classification number: H03M1/12 , G06F13/4022 , G06F13/4282 , H03M1/0872 , H03M1/0881 , H03M1/188
Abstract: In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths and a controller. The plurality of processing paths may include a static processing path configured to generate a first digital signal based on an analog input signal and a dynamic processing path configured to generate a second digital signal based on the analog input signal, wherein a parameter of the dynamic processing path is determined based on a characteristic of the analog input signal. The controller may be configured to select the first digital signal as a digital output signal of the processing system when a change is occurring to the characteristic and select the second digital signal as the digital output signal in the absence of change occurring to the characteristic.
-
Patent Agency Ranking
公开(公告)号：US20230031363A1
公开(公告)日：2023-02-02
申请号：US17573000
申请日：2022-01-11
Inventor： Saurabh SINGH , Chandra B. PRAKASH
Abstract: A method may include receiving, by a calibration circuit, an output of a subsystem comprising the sensor and the analog front end. The method may further include separating the output individually into the sensor offset and the amplifier offset by using inherent properties of separate frequency ranges for the sensor offset and the amplifier offset. The method may also include calibrating, by the calibration circuit, the sensor offset by determining a first calibration value for the sensor offset such that the output approximates zero during an idle-channel condition. The method may additionally include calibrating, by the calibration circuit, the amplifier offset by determining a second calibration value for the amplifier offset such that the output approximates zero during the idle-channel condition.
-
公开(公告)号：US20230003779A1
公开(公告)日：2023-01-05
申请号：US17668445
申请日：2022-02-10
Inventor： Saurabh SINGH , Chandra B. PRAKASH , Eric KIMBALL , Cory J. PETERSON , Ryan LOBO
IPC: G01R27/08
Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
-
公开(公告)号：US20210351753A1
公开(公告)日：2021-11-11
申请号：US17233811
申请日：2021-04-19
Inventor： John B. BOWLERWELL , Andrew J. HOWLETT , Saurabh SINGH , Andrew BUIST
Abstract: The present disclosure relates to circuitry for providing an output voltage. The circuitry comprises: voltage generator circuitry configured to provide an output voltage to an output node of the circuitry; current limiter circuitry operable to perform current limiting so as to limit a current supplied at the output node of the circuitry; detection circuitry configured to output a detection signal when a load voltage across a load coupled to the output node of the circuitry reaches a target voltage; and delay circuitry configured to receive the detection signal and to output a control signal to deactivate current limiting by the current limiter circuitry after a predetermined delay period after receiving the detection signal.
-
公开(公告)号：US20220353970A1
公开(公告)日：2022-11-03
申请号：US17860918
申请日：2022-07-08
Inventor： Dave SMITH , Saurabh SINGH , Andrew BUIST , Paulius CEREBIEJUS , Mark J. MCCLOY-STEVENS , Terence A. ORR
IPC: H05B45/345 , H03F3/04
Abstract: The present disclosure relates to current control circuitry for controlling a current through a load, the current control circuitry comprising: amplifier circuitry; reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry; an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; a current output terminal; a clock-controlled variable resistance coupled to the current output terminal of the output stage, wherein a resistance of the variable resistance is based on a digital code input to the variable resistance; and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.
-
公开(公告)号：US20180046239A1
公开(公告)日：2018-02-15
申请号：US15233624
申请日：2016-08-10
Inventor： Edmund Mark SCHNEIDER , Daniel J. ALLEN , Saurabh SINGH , Aniruddha SATOSKAR
Abstract: A system may include a plurality of processing paths and a controller. The processing paths may include a first processing path configured to generate a first digital signal based on an analog input signal and one or more other processing paths each configured to consume a smaller amount of power than the first processing path, and each configured to generate a respective digital signal based on the analog input signal, wherein one of the other processing paths has a noise floor based on fidelity characteristics of the analog input signal or subsequent processing requirements of a digital output signal generated from at least one of the first digital signal and the respective digital signals. The controller may be configured to select one of the first digital signal and the respective digital signals as the digital output signal of the processing system based on a magnitude of the analog input signal.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.019 seconds)
