摘要:
A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
摘要:
Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which the nanotubes of the channel region are substantially all of the same semiconducting type of nanotubes. At least one gate is formed in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region. Forming a channel region includes forming a fabric of nanotubes in which the fabric has both semiconducting and metallic nanotubes and the fabric is processed to remove substantially all of the metallic nanotubes.
摘要:
A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.
摘要:
A two terminal memory device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes stimulus circuitry in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.
摘要:
A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.
摘要:
A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
摘要:
A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
摘要:
Under one aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes. The cathode and anode are in fixed and direct physical contact, and are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode. In some embodiments, the anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric may have a thickness, e.g., of 0.5 to 20 nm. Or, the non-woven nanotube fabric may include a block of nanotubes. The nanotubes may include metallic nanotubes and semiconducting nanotubes, and the cathode may include an n-type semiconductor material. A Schottky barrier can form between the n-type semiconductor material and the metallic nanotubes and/or a PN junction can form between the n-type semiconductor material and the semiconducting nanotubes.
摘要:
A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
摘要:
A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.