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    Universal adiabatic quantum computing with superconducting qubits
    11.
    发明授权
    Universal adiabatic quantum computing with superconducting qubits 有权

    公开(公告)号：US11348024B2

    公开(公告)日：2022-05-31

    申请号：US16029040

    申请日：2018-07-06

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Richard G. Harris ,  Mohammad H. Amin ,  Anatoly Smirnov

    IPC: G06N10/00 ,  H03K3/38 ,  H03K19/195 ,  G11C11/44

    Abstract: A quantum processor is operable as a universal adiabatic quantum computing system. The quantum processor includes physical qubits, with at least a first and second communicative coupling available between pairs of qubits via an in-situ tunable superconducting capacitive coupler and an in-situ tunable superconducting inductive coupler, respectively. Tunable couplers provide diagonal and off-diagonal coupling. Compound Josephson junctions (CJJs) of the tunable couplers are responsive to a flux bias to tune a sign and magnitude of a sum of a capacitance of a fixed capacitor and a tunable capacitance which is mediated across a pair of coupling capacitors. The qubits may be hybrid qubits, operable in a flux regime or a charge regime. Qubits may include a pair of CJJs that interrupt a loop of material and which are separated by an island of superconducting material which is voltage biased with respect to a qubit body.

    SYSTEMS AND METHODS FOR DEGENERACY MITIGATION IN A QUANTUM PROCESSOR
    12.
    发明申请
    SYSTEMS AND METHODS FOR DEGENERACY MITIGATION IN A QUANTUM PROCESSOR 有权

    公开(公告)号：US20210350269A1

    公开(公告)日：2021-11-11

    申请号：US17379172

    申请日：2021-07-19

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Andrew Douglas King ,  Alexandre Fréchette ,  Evgeny A. Andriyash ,  Trevor Michael Lanting ,  Emile M. Hoskinson ,  Mohammad H. Amin

    IPC: G06N10/00

    Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

    RE-EQUILIBRATED QUANTUM SAMPLING
    14.
    发明申请
    RE-EQUILIBRATED QUANTUM SAMPLING 审中-公开

    公开(公告)号：US20180196780A1

    公开(公告)日：2018-07-12

    申请号：US15870411

    申请日：2018-01-12

    Applicant: D-Wave Systems Inc.

    Inventor： Mohammad H. Amin ,  Evgeny A. Andriyash

    IPC: G06F17/17 ,  G06F17/18 ,  G06F5/01 ,  G06N99/00 ,  G06F17/13 ,  G06F9/30

    CPC classification number: G06F17/17 ,  G06F5/01 ,  G06F9/30145 ,  G06F17/13 ,  G06F17/18 ,  G06N7/005 ,  G06N10/00 ,  H04L9/0852

    Abstract: The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples maybe used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor with a fast ramp operation, and reading out states for the qubits. The state for the qubits may be post processes and/or used to calculate importance weights.

    Topologically protected qubits, processors with topologically protected qubits, and methods for use of topologically protected qubits
    15.
    发明授权
    Topologically protected qubits, processors with topologically protected qubits, and methods for use of topologically protected qubits 有权

    公开(公告)号：US12224750B2

    公开(公告)日：2025-02-11

    申请号：US17883874

    申请日：2022-08-09

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. Amin ,  Richard G. Harris

    IPC: H03K19/195 ,  G06N10/40

    Abstract: A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.

    System and methods for achieving orthogonal control of non-orthogonal qubit parameters
    16.
    发明授权
    System and methods for achieving orthogonal control of non-orthogonal qubit parameters 有权

    公开(公告)号：US12190203B2

    公开(公告)日：2025-01-07

    申请号：US18385226

    申请日：2023-10-30

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Mohammad H. Amin ,  Trevor Michael Lanting ,  Colin Enderud

    IPC: G06N10/00

    Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.

    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS WITH IMPROVED COHERENCE
    17.
    发明公开
    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS WITH IMPROVED COHERENCE 审中-公开

    公开(公告)号：US20240237555A9

    公开(公告)日：2024-07-11

    申请号：US18277688

    申请日：2022-02-17

    Applicant: D-WAVE SYSTEMS INC.

    Inventor： Colin C. Enderud ,  Mohammad H. Amin ,  Loren J. Swenson

    IPC: H10N60/01 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

    CPC classification number: H10N60/0912 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53285 ,  H01L25/18 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

    Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.

    Systems and methods for coupling qubits in a quantum processor
    19.
    发明授权
    Systems and methods for coupling qubits in a quantum processor 有权

    公开(公告)号：US11494683B2

    公开(公告)日：2022-11-08

    申请号：US16955526

    申请日：2018-12-19

    Applicant: D-Wave Systems Inc.

    Inventor： Mohammad H. Amin ,  Paul I. Bunyk ,  Trevor M. Lanting ,  Chunqing Deng ,  Anatoly Smirnov ,  Kelly T. R. Boothby ,  Emile M. Hoskinson ,  Christopher B. Rich

    IPC: H01L39/02 ,  G06N10/00 ,  H01L39/22

    Abstract: Josephson junctions (JJ) may replace primary inductance of transformers to realize galvanic coupling between qubits, advantageously reducing size. A long-range symmetric coupler may include a compound JJ (CJJ) positioned at least approximately at a half-way point along the coupler to advantageously provide a higher energy of a first excited state than that of an asymmetric long-range coupler. Quantum processors may include qubits and couplers with a non-stoquastic Hamiltonian to enhance multi-qubit tunneling during annealing. Qubits may include additional shunt capacitances, e.g., to increase overall quality of a total capacitance and improve quantum coherence. A sign and/or magnitude of an effective tunneling amplitude Δeff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).

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