公开(公告)号：US10062747B2

公开(公告)日：2018-08-28

申请号：US15573200

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Youngshin Eum ,  Kazuhiro Oyama ,  Yasushi Higuchi ,  Shinichi Hoshi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778 ,  H01L29/812 ,  H01L29/20 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/06 ,  H01L29/0615 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/812

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

公开(公告)号：US09711638B2

公开(公告)日：2017-07-18

申请号：US15039505

申请日：2014-11-25

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Toshiharu Makino ,  Masahiko Ogura ,  Hiromitsu Kato ,  Daisuke Takeuchi ,  Satoshi Yamasaki ,  Norio Tokuda ,  Takao Inokuma ,  Takuma Minamiyama

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/47 ,  H01L29/872 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7813 ,  H01L29/1602 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66045 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/872

Abstract: A semiconductor device includes a MISFET having: a diamond substrate; a drift layer having a first layer with a first density for providing a hopping conduction and a second layer with a second density lower than the first density, and having a δ dope structure; a body layer on the drift layer; a source region in an upper portion of the body layer; a gate insulation film on a surface of the body layer; a gate electrode on a surface of the gate insulation film; a first electrode electrically connected to the source region and a channel region; and a second electrode electrically connected to the diamond substrate. The MISFET flows current in the drift layer in a vertical direction, and the current flows between the first electrode and the second electrode.

公开(公告)号：US20150115316A1

公开(公告)日：2015-04-30

申请号：US14391197

申请日：2013-04-17

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Masakiyo Sumitomo ,  Yasushi Higuchi

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L27/0722 ,  H01L27/0727 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7827 ,  H01L29/861

Abstract: A semiconductor device includes: a drift layer having a first conduction type; a base layer having a second conduction type and formed on the drift layer; an emitter layer having the first conduction type and formed in a surface layer portion of the base layer; a buffer layer having the first conduction type and formed in the drift layer separated from the base layer; a collector layer having the second conduction type and formed selectively in the buffer layer; a gate insulation film in contact with a channel region of the base layer between the drift layer and the emitter layer; a gate electrode formed on the gate insulation film; a first electrode electrically connected to the base layer and the emitter layer; and a second electrode electrically connected to the buffer layer and the collector layer. The buffer layer has a carrier density smaller than a space charge density.

Abstract translation: 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型并形成在漂移层上的基极层; 具有第一导电类型并形成在基底层的表层部分中的发射极层; 具有第一导电类型并形成在与基底层分离的漂移层中的缓冲层; 具有第二导电类型并且选择性地形成在缓冲层中的集电极层; 与漂移层和发射极层之间的基底层的沟道区域接触的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 电连接到所述基极层和所述发射极层的第一电极; 以及与所述缓冲层和所述集电体层电连接的第二电极。 缓冲层具有小于空间电荷密度的载流子密度。

公开(公告)号：US20150061090A1

公开(公告)日：2015-03-05

申请号：US14386099

申请日：2013-04-17

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama

IPC: H01L29/868 ,  H01L29/10

CPC classification number: H01L29/868 ,  H01L29/08 ,  H01L29/1095 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor device includes: a drift layer having a first conductive type; a first semiconductor layer having a second conductive type and arranged in a surface portion of the drift layer; a second semiconductor layer having the first conductive type, arranged at a position of the drift layer spaced apart from the first semiconductor layer, and having a carrier density larger than the drift layer; a hole injection layer having the second conductive type and arranged selectively in the second semiconductor layer; a first electrode electrically connecting to the first semiconductor layer; a second electrode electrically connecting to the second semiconductor layer and the hole injection layer. The second semiconductor layer has a carrier density smaller than a spatial charge density.

Abstract translation: 一种半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型且布置在所述漂移层的表面部分中的第一半导体层; 具有第一导电类型的第二半导体层，布置在与第一半导体层间隔开的漂移层的位置处，并且具有大于漂移层的载流子密度; 具有第二导电类型且选择性地布置在第二半导体层中的空穴注入层; 电连接到第一半导体层的第一电极; 电连接到第二半导体层和空穴注入层的第二电极。 第二半导体层具有小于空间电荷密度的载流子密度。