公开(公告)号：US10186606B2

公开(公告)日：2019-01-22

申请号：US15537644

申请日：2016-01-13

Applicant: DENSO CORPORATION

Inventor： Masakiyo Sumitomo

IPC: H01L29/739 ,  H01L27/07 ,  H01L21/761 ,  H01L27/04 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.

公开(公告)号：US09231090B2

公开(公告)日：2016-01-05

申请号：US14375895

申请日：2013-02-18

Applicant: DENSO CORPORATION

Inventor： Yasushi Higuchi ,  Masakiyo Sumitomo

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7393 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7825

Abstract: In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.

Abstract translation: 在沟槽栅型绝缘栅双极晶体管中，电流不会向下流到沟槽的下部，即使施加高电压，也抑制沟槽下部的高电场，例如在 关断时间，抑制导通电阻的上升和耐击穿电压和耐电压的降低。 在半导体器件中，设置多个沟槽到达漂移层的后表面，并且集电极层设置在漂移层的表面层部分中的沟槽的延伸方向的前端侧。 当施加预定电压的栅电极时，在接触沟槽的基底层的一部分中形成沟道区，并且电流沿着沟槽沿预定方向流动。

公开(公告)号：US09515067B2

公开(公告)日：2016-12-06

申请号：US14513685

申请日：2014-10-14

Applicant: DENSO CORPORATION

Inventor： Hirotaka Saikaku ,  Tsuyoshi Yamamoto ,  Shoji Mizuno ,  Masakiyo Sumitomo ,  Tetsuo Fujii ,  Jun Sakakibara ,  Hitoshi Yamaguchi ,  Yoshiyuki Hattori ,  Rie Taguchi ,  Makoto Kuwahara

IPC: H01L29/66 ,  H01L27/148 ,  H01L27/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/861 ,  H02M7/00

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4983 ,  H01L29/66734 ,  H01L29/7391 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7805 ,  H01L29/7819 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/861 ,  H01L2924/0002 ,  H02M7/003 ,  H01L2924/00

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract translation: 一种半导体器件包括：具有漂移层的开关元件; 基地区 在基极区域中的元件侧第一杂质区域; 夹在所述第一杂质区域和所述漂移层之间的元件侧栅电极; 接触漂移层的第二杂质区; 与元件侧第一杂质区域和基极区域耦合的元件侧第一电极; 以及与所述第二杂质区域耦合的元件侧第二电极以及具有：第一导电层的FWD; 第二导电层; 耦合到所述第二导电层的二极管侧第一电极; 耦合到所述第一导电层的二极管侧第二电极; 第二导电层中的二极管侧第一杂质区; 以及夹在第一杂质区域和第一导电层之间的第二导电层中的二极管侧栅电极，并具有作为过剩载流子注入抑制栅极的第一栅极电极。

公开(公告)号：US20150115314A1

公开(公告)日：2015-04-30

申请号：US14381238

申请日：2013-03-04

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi ,  Kazuhiro Oyama

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/42376 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7397

Abstract: In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced.

Abstract translation: 在半导体器件中，沟槽包括在基底层的表面上具有开口部分的第一沟槽和与第一沟槽连通并且相对的侧壁之间的距离大于相对侧壁的第二沟槽 的第一沟槽和底部部分位于漂移层中。 连接到第一沟槽的第二沟槽的连接部分的壁表面是圆形的。 因此，可以抑制在第一沟槽和第二沟槽之间的连接部分附近出现大的电场集中。 此外，当从沟道区域向漂移层提供电子时，在连接部附近电子的流动方向不会急剧变化。 因此，可以降低导通电阻。

公开(公告)号：US12283593B2

公开(公告)日：2025-04-22

申请号：US17903113

申请日：2022-09-06

Applicant: DENSO CORPORATION

Inventor： Shuichi Toriyama ,  Masakiyo Sumitomo ,  Tasbir Rahman

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/872

Abstract: A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.

公开(公告)号：US10763345B2

公开(公告)日：2020-09-01

申请号：US16393006

申请日：2019-04-24

Applicant: DENSO CORPORATION

Inventor： Koichi Murakawa ,  Masakiyo Sumitomo ,  Shigeki Takahashi

IPC: H01L29/739 ,  H01L29/861 ,  H01L29/06 ,  H01L27/07 ,  H01L29/10 ,  H01L29/78 ,  H01L29/868

Abstract: In a semiconductor device, a boundary area is between an IGBT region and a diode region. In other words, the boundary region is at a position adjacent to the diode region. The boundary region has a lower ratio of formation of a high-concentration P-type layer than the IGBT region. Accordingly, during recovery, hole injection from the IGBT region to the diode region can be inhibited. The reduced ratio of formation of the high-concentration P-type layer in the boundary region also reduces the amount of hole injection from the high-concentration P-type layer of the boundary region. Thus, it inhibits an increase in maximum reverse current during the recovery, and also decreases the carrier density on the cathode side to inhibit an increase in tail electrical current, so that the semiconductor device reduces switching loss and is highly resistant to recovery destruction.

公开(公告)号：US10748988B2

公开(公告)日：2020-08-18

申请号：US16504858

申请日：2019-07-08

Applicant: DENSO CORPORATION

Inventor： Masanori Miyata ,  Shigeki Takahashi ,  Masakiyo Sumitomo ,  Tomofusa Shiga

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/737 ,  H01L29/66 ,  H01L27/082 ,  H01L29/732 ,  H01L29/423

Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.

公开(公告)号：US20150115316A1

公开(公告)日：2015-04-30

申请号：US14391197

申请日：2013-04-17

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Masakiyo Sumitomo ,  Yasushi Higuchi

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L27/0722 ,  H01L27/0727 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7827 ,  H01L29/861

Abstract: A semiconductor device includes: a drift layer having a first conduction type; a base layer having a second conduction type and formed on the drift layer; an emitter layer having the first conduction type and formed in a surface layer portion of the base layer; a buffer layer having the first conduction type and formed in the drift layer separated from the base layer; a collector layer having the second conduction type and formed selectively in the buffer layer; a gate insulation film in contact with a channel region of the base layer between the drift layer and the emitter layer; a gate electrode formed on the gate insulation film; a first electrode electrically connected to the base layer and the emitter layer; and a second electrode electrically connected to the buffer layer and the collector layer. The buffer layer has a carrier density smaller than a space charge density.

Abstract translation: 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型并形成在漂移层上的基极层; 具有第一导电类型并形成在基底层的表层部分中的发射极层; 具有第一导电类型并形成在与基底层分离的漂移层中的缓冲层; 具有第二导电类型并且选择性地形成在缓冲层中的集电极层; 与漂移层和发射极层之间的基底层的沟道区域接触的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 电连接到所述基极层和所述发射极层的第一电极; 以及与所述缓冲层和所述集电体层电连接的第二电极。 缓冲层具有小于空间电荷密度的载流子密度。

公开(公告)号：US20150048413A1

公开(公告)日：2015-02-19

申请号：US14386132

申请日：2013-05-13

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift layer; a base layer arranged in a surface portion of the drift layer; multiple trenches penetrating the base layer and reaching the drift layer; and a gate electrode arranged on the gate insulation film in each trench. Each trench includes: a first trench having an opening on a surface of the base layer; and a second trench connecting the first trench and having a portion, of which a distance between facing sidewalls of the second trench is longer than a distance between facing sidewalls of the first trench. The opening of each first trench is sealed with the gate electrode. An inside of each gate electrode includes a cavity portion.

Abstract translation: 半导体器件包括：漂移层; 布置在所述漂移层的表面部分中的基底层; 多个沟槽穿透基层并到达漂移层; 以及在每个沟槽中布置在栅极绝缘膜上的栅电极。 每个沟槽包括：在基底层的表面上具有开口的第一沟槽; 以及第二沟槽，其连接所述第一沟槽并具有一部分，所述第二沟槽的所述第二沟槽的相对侧壁之间的距离比所述第一沟槽的相对侧壁之间的距离长。 每个第一沟槽的开口用栅电极密封。 每个栅电极的内部包括空腔部分。

公开(公告)号：US11289476B2

公开(公告)日：2022-03-29

申请号：US16833977

申请日：2020-03-30

Applicant: DENSO CORPORATION

Inventor： Koichi Murakawa ,  Shigeki Takahashi ,  Masakiyo Sumitomo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/861

Abstract: In a semiconductor device in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed to a semiconductor substrate, a plurality of carrier injection layers electrically connected with a second electrode and configuring a PN junction with a field stop layer is disposed in a cathode layer. When an impurity concentration of the field stop layer is defined as Nfs [cm−3], and a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L1 [μm], the plurality of carrier injection layers satisfies a relationship of L1>6.8×10−16×Nfs+20.