公开(公告)号：US10403745B2

公开(公告)日：2019-09-03

申请号：US15578403

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Yasushi Higuchi ,  Shinichi Hoshi ,  Kazuhiro Oyama

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L29/10

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

公开(公告)号：US20150115314A1

公开(公告)日：2015-04-30

申请号：US14381238

申请日：2013-03-04

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi ,  Kazuhiro Oyama

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/42376 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7397

Abstract: In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced.

Abstract translation: 在半导体器件中，沟槽包括在基底层的表面上具有开口部分的第一沟槽和与第一沟槽连通并且相对的侧壁之间的距离大于相对侧壁的第二沟槽 的第一沟槽和底部部分位于漂移层中。 连接到第一沟槽的第二沟槽的连接部分的壁表面是圆形的。 因此，可以抑制在第一沟槽和第二沟槽之间的连接部分附近出现大的电场集中。 此外，当从沟道区域向漂移层提供电子时，在连接部附近电子的流动方向不会急剧变化。 因此，可以降低导通电阻。

公开(公告)号：US20140339602A1

公开(公告)日：2014-11-20

申请号：US14375895

申请日：2013-02-18

Applicant: DENSO CORPORATION

Inventor： Yasushi Higuchi ,  Masakiyo Sumitomo

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7393 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7825

Abstract: In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.

Abstract translation: 在沟槽栅型绝缘栅双极晶体管中，电流不会向下流到沟槽的下部，即使施加高电压，也抑制沟槽下部的高电场，例如在 关断时间，抑制导通电阻的上升和耐击穿电压和耐电压的降低。 在半导体器件中，设置多个沟槽到达漂移层的后表面，并且集电极层设置在漂移层的表面层部分中的沟槽的延伸方向的前端侧。 当施加预定电压的栅电极时，在接触沟槽的基底层的一部分中形成沟道区，并且电流沿着沟槽沿预定方向流动。

公开(公告)号：US10062747B2

公开(公告)日：2018-08-28

申请号：US15573200

申请日：2016-06-14

Applicant: DENSO CORPORATION

Inventor： Youngshin Eum ,  Kazuhiro Oyama ,  Yasushi Higuchi ,  Shinichi Hoshi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/778 ,  H01L29/812 ,  H01L29/20 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/06 ,  H01L29/0615 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/812

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

公开(公告)号：US20150115316A1

公开(公告)日：2015-04-30

申请号：US14391197

申请日：2013-04-17

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Masakiyo Sumitomo ,  Yasushi Higuchi

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L27/0722 ,  H01L27/0727 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7397 ,  H01L29/7827 ,  H01L29/861

Abstract: A semiconductor device includes: a drift layer having a first conduction type; a base layer having a second conduction type and formed on the drift layer; an emitter layer having the first conduction type and formed in a surface layer portion of the base layer; a buffer layer having the first conduction type and formed in the drift layer separated from the base layer; a collector layer having the second conduction type and formed selectively in the buffer layer; a gate insulation film in contact with a channel region of the base layer between the drift layer and the emitter layer; a gate electrode formed on the gate insulation film; a first electrode electrically connected to the base layer and the emitter layer; and a second electrode electrically connected to the buffer layer and the collector layer. The buffer layer has a carrier density smaller than a space charge density.

Abstract translation: 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型并形成在漂移层上的基极层; 具有第一导电类型并形成在基底层的表层部分中的发射极层; 具有第一导电类型并形成在与基底层分离的漂移层中的缓冲层; 具有第二导电类型并且选择性地形成在缓冲层中的集电极层; 与漂移层和发射极层之间的基底层的沟道区域接触的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 电连接到所述基极层和所述发射极层的第一电极; 以及与所述缓冲层和所述集电体层电连接的第二电极。 缓冲层具有小于空间电荷密度的载流子密度。

公开(公告)号：US20150048413A1

公开(公告)日：2015-02-19

申请号：US14386132

申请日：2013-05-13

Applicant: DENSO CORPORATION

Inventor： Kazuki Arakawa ,  Masakiyo Sumitomo ,  Masaki Matsui ,  Yasushi Higuchi

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift layer; a base layer arranged in a surface portion of the drift layer; multiple trenches penetrating the base layer and reaching the drift layer; and a gate electrode arranged on the gate insulation film in each trench. Each trench includes: a first trench having an opening on a surface of the base layer; and a second trench connecting the first trench and having a portion, of which a distance between facing sidewalls of the second trench is longer than a distance between facing sidewalls of the first trench. The opening of each first trench is sealed with the gate electrode. An inside of each gate electrode includes a cavity portion.

Abstract translation: 半导体器件包括：漂移层; 布置在所述漂移层的表面部分中的基底层; 多个沟槽穿透基层并到达漂移层; 以及在每个沟槽中布置在栅极绝缘膜上的栅电极。 每个沟槽包括：在基底层的表面上具有开口的第一沟槽; 以及第二沟槽，其连接所述第一沟槽并具有一部分，所述第二沟槽的所述第二沟槽的相对侧壁之间的距离比所述第一沟槽的相对侧壁之间的距离长。 每个第一沟槽的开口用栅电极密封。 每个栅电极的内部包括空腔部分。

公开(公告)号：US10714606B2

公开(公告)日：2020-07-14

申请号：US15753342

申请日：2016-09-05

Applicant: DENSO CORPORATION

Inventor： Youngshin Eum ,  Kazuhiro Oyama ,  Yasushi Higuchi ,  Yoshinori Tsuchiya ,  Shinichi Hoshi

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/812 ,  H01L29/205 ,  H01L29/872 ,  H01L29/40 ,  H01L29/20 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm−2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

公开(公告)号：US10109727B2

公开(公告)日：2018-10-23

申请号：US15531015

申请日：2015-12-08

Applicant: DENSO CORPORATION

Inventor： Kazuhiro Oyama ,  Yasushi Higuchi ,  Seigo Oosawa ,  Masaki Matsui ,  Youngshin Eum

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/786 ,  H01L29/06 ,  H01L29/51 ,  H01L29/40 ,  H01L29/423 ,  H01L29/20

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

公开(公告)号：US09231090B2

公开(公告)日：2016-01-05

申请号：US14375895

申请日：2013-02-18

Applicant: DENSO CORPORATION

Inventor： Yasushi Higuchi ,  Masakiyo Sumitomo

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7393 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7824 ,  H01L29/7825

Abstract: In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.

Abstract translation: 在沟槽栅型绝缘栅双极晶体管中，电流不会向下流到沟槽的下部，即使施加高电压，也抑制沟槽下部的高电场，例如在 关断时间，抑制导通电阻的上升和耐击穿电压和耐电压的降低。 在半导体器件中，设置多个沟槽到达漂移层的后表面，并且集电极层设置在漂移层的表面层部分中的沟槽的延伸方向的前端侧。 当施加预定电压的栅电极时，在接触沟槽的基底层的一部分中形成沟道区，并且电流沿着沟槽沿预定方向流动。