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    Semiconductor device and production method thereof
    11.
    发明授权
    Semiconductor device and production method thereof 有权

    公开(公告)号：US10985241B2

    公开(公告)日：2021-04-20

    申请号：US16339223

    申请日：2017-09-26

    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

    Inventor： Hiromichi Kinpara ,  Yusuke Yamashita ,  Yasushi Urakami

    IPC: H01L29/06 ,  H01L21/04 ,  H01L21/761 ,  H01L29/16 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

    Abstract: A semiconductor device includes a semiconductor substrate, which includes an element region and an outer-periphery voltage withstanding region. The outer-periphery voltage withstanding region includes a plurality of p-type guard rings surrounding the element region in a multiple manner. Each of the guard rings includes a high concentration region and a low concentration region. A low concentration region of an outermost guard ring includes a first part positioned on an outer peripheral side of its high concentration region. Respective low concentration regions of the guard rings include respective second parts, each positioned in a range sandwiched between corresponding two adjacent high concentration regions among a plurality of concentration regions. A width of the first part on a front surface is wider than widths of the second parts on the front surface.

    SiC-MOSFET and method of manufacturing the same
    12.
    发明授权
    SiC-MOSFET and method of manufacturing the same 有权

    公开(公告)号：US10770579B2

    公开(公告)日：2020-09-08

    申请号：US15816697

    申请日：2017-11-17

    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

    Inventor： Hidefumi Takaya ,  Yasushi Urakami ,  Yukihiko Watanabe

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417

    Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

    SIC SINGLE CRYSTAL, SIC WAFER, AND SEMICONDUCTOR DEVICE
    14.
    发明申请
    SIC SINGLE CRYSTAL, SIC WAFER, AND SEMICONDUCTOR DEVICE 有权
    SIC单晶，SIC晶圆和半导体器件

    公开(公告)号：US20140291700A1

    公开(公告)日：2014-10-02

    申请号：US14353710

    申请日：2012-12-03

    Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

    Inventor： Itaru Gunjishima ,  Yasushi Urakami ,  Ayumu Adachi

    IPC: H01L29/04 ,  C30B29/36 ,  H01L29/16

    CPC classification number: H01L29/045 ,  C30B23/025 ,  C30B29/36 ,  H01L29/1608

    Abstract: An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal.

    Abstract translation: SiC单晶包括低位错密度区域（A），其中位错密度在{0001}面内方向（主要是平行于<11-20>方向的方向）上具有汉堡矢量不是 超过3700厘米/厘米3。 这样的SiC单晶通过以下方式获得：从a平面生长的晶体切割高偏移角的c面生长晶种; 应用c面生长，使得引入c面平面的螺旋位错的密度可能落在规定的范围内; 从得到的c面生长晶体中切出低偏移角的c面生长晶体; 并施加c面生长，使得引入c面小面的螺旋位错的密度可能落在规定的范围内。 从这种SiC单晶中获得SiC晶片和半导体器件。

    Semiconductor device having cell section with gate structures partly covered with protective film
    15.
    发明授权
    Semiconductor device having cell section with gate structures partly covered with protective film 有权

    公开(公告)号：US12100763B2

    公开(公告)日：2024-09-24

    申请号：US17482840

    申请日：2021-09-23

    Applicant: DENSO CORPORATION

    Inventor： Yasushi Urakami ,  Jun Saito ,  Yusuke Yamashita

    IPC: H01L29/78 ,  H01L29/10

    CPC classification number: H01L29/7813 ,  H01L29/1095

    Abstract: A semiconductor device includes a cell section having a plurality of gate structures, and an outer peripheral section surrounding the cell section. The cell section includes a semiconductor substrate, the plurality of gate structures, a first electrode and a second electrode. The cell section and the outer peripheral section includes a protective film made of a material having a thermal conductivity lower than that of the first electrode. The protective film extends from the outer peripheral section to an outer edge portion of the cell section adjacent to the outer peripheral section and covers a portion of the first electrode adjacent to the outer peripheral section.

    Semiconductor switching element
    17.
    发明授权
    Semiconductor switching element 有权

    公开(公告)号：US10367091B2

    公开(公告)日：2019-07-30

    申请号：US16075840

    申请日：2016-12-26

    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

    Inventor： Jun Saito ,  Sachiko Aoi ,  Yasushi Urakami

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/08 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/10 ,  H01L29/417

    Abstract: A trench gate semiconductor switching element is provided. The semiconductor substrate of the element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench, and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region. The bottom region includes a first bottom region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench and extending from the bottom surface to a first position; and a second bottom region in contact with the gate insulation layer in a second range adjacent to the first range and extending from the bottom surface to a second position lower than the first position.

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