公开(公告)号：US20170263757A1

公开(公告)日：2017-09-14

申请号：US15505267

申请日：2015-09-08

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Hirotaka SAIKAKU ,  Jun SAKAKIBARA ,  Shoji MIZUNO ,  Yuichi TAKEUCHI

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L21/047 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

公开(公告)号：US20160104794A1

公开(公告)日：2016-04-14

申请号：US14894668

申请日：2014-05-28

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Jun MORIMOTO ,  Narumasa SOEJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/041 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide semiconductor device includes: a vertical MOSFET having: a semiconductor substrate including a high-concentration impurity layer and a drift layer; a base region; a source region; a trench gate structure; a source electrode; and a drain electrode. The base region has a high-concentration base region and a low-concentration base region having a second conductivity type with an impurity concentration lower than the high-concentration base region, which are stacked each other. Each of the high-concentration base region and the low-concentration base region contacts a side surface of the trench.

Abstract translation: 碳化硅半导体器件包括：垂直MOSFET，具有：包括高浓度杂质层和漂移层的半导体衬底; 基地区 源区; 沟槽门结构; 源电极; 和漏电极。 基极区域具有彼此堆叠的高浓度基极区域和具有杂质浓度低于高浓度基极区域的第二导电类型的低浓度基极区域。 高浓度基区和低浓度基区各自与沟槽的侧面接触。

公开(公告)号：US20210324517A1

公开(公告)日：2021-10-21

申请号：US17364604

申请日：2021-06-30

Applicant: DENSO CORPORATION

Inventor： Hiroaki FUJIBAYASHI ,  Yuichi TAKEUCHI

IPC: C23C16/455 ,  C23C16/32

Abstract: A semiconductor manufacturing device includes: a thin film formation portion that includes a chamber; and a supply gas unit that introduces a supply gas into the chamber. The supply gas unit includes: multiple supply pipes; a raw material flow rate controller that is installed on each of the multiple supply pipes, and controls a flow rate; a collective pipe that is connected to the multiple supply pipes, and generates a mixed gas; multiple distribution pipes connected to a downstream side of the collective pipe; a pressure controller that is installed on one distribution pipe, and adjusts a mixed gas pressure; and a distribution flow rate controller that is installed on a distribution pipe different from the distribution pipe provided with the pressure controller, and controls a flow rate of the mixed gas.

公开(公告)号：US20190341484A1

公开(公告)日：2019-11-07

申请号：US16516329

申请日：2019-07-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Yu SUZUKI ,  Masahiro SUGIMOTO ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/04 ,  H01L21/761 ,  H01L21/765 ,  H01L29/66

Abstract: A silicon carbide semiconductor device includes: a main cell region; a sense cell region; a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate having a high impurity concentration layer and a drift layer; an element isolation layer arranged between the main cell region and the sense cell region, and surrounding the sense cell region; and a plurality of electric field relaxation layers arranged between the main cell region and the sense cell region. The MOSFET includes: a base region; a source region; a plurality of deep layers; a trench gate structure; a source electrode; and a drain electrode. The deep layers and the electric field relaxation layers are arranged in a stripe pattern at a predetermined interval.

公开(公告)号：US20190035883A1

公开(公告)日：2019-01-31

申请号：US16069927

申请日：2017-01-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04

Abstract: A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate that includes a foundation layer; forming a deep trench in the foundation layer; and filling the deep trench with a deep layer having a second conductive type and a limiting layer having the first conductive type. In the filling the deep trench, growth of the deep layer from a bottom of the deep trench toward an opening inlet of the deep trench and growth of the limiting layer from a side face of the deep trench are achieved by: dominant epitaxial growth of a second conductive type layer over a first conductive type layer on the bottom of the deep trench; and dominant epitaxial growth of the first conductive type layer over the second conductive type layer on the side face of the deep trench, based on plane orientation dependency of the compound semiconductor during epitaxial growth.

公开(公告)号：US20190013392A1

公开(公告)日：2019-01-10

申请号：US16069622

申请日：2017-01-19

Applicant: DENSO CORPORATION

Inventor： Yuichi TAKEUCHI ,  Katsumi SUZUKI ,  Yusuke YAMASHITA

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/66068 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/7813

Abstract: A method for manufacturing a compound semiconductor device includes causing epitaxial growth of a p-type impurity layer containing a compound semiconductor on a foundation layer containing the compound semiconductor. The causing the epitaxial growth includes performing pre-doping to preliminarily introduce dopant gas before introducing material gas for the epitaxial growth of the compound semiconductor. The dopant gas contains an organic metal material providing dopant of p-type impurities. An impurity concentration profile of the p-type impurity layer is controlled by controlling a time of the pre-doping.

公开(公告)号：US20170317162A1

公开(公告)日：2017-11-02

申请号：US15518616

申请日：2015-12-11

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Shinya NISHIMURA ,  Hirokazu FUJIWARA ,  Narumasa SOEJIMA ,  Yuichi TAKEUCHI

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20170012109A1

公开(公告)日：2017-01-12

申请号：US15113484

申请日：2015-01-14

Applicant: DENSO CORPORATION

Inventor： Nozomu AKAGI ,  Jun SAKAKIBARA ,  Shoji MIZUNO ,  Yuichi TAKEUCHI

IPC: H01L29/66 ,  H01L21/04 ,  H01L23/544 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/66068 ,  H01L21/0465 ,  H01L21/0475 ,  H01L23/544 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.

Abstract translation: 一种制造SiC半导体器件的方法包括：通过在将掩模布置在其上之后通过使用掩模进行蚀刻部分去除漂移层的顶部而在与基板的表面平行的横截面上形成彼此分离的凹槽 漂移层的前表面; 通过使用掩模在每个凹部的底部上离子注入第二导电型杂质，形成具有第二导电类型的电场弛豫层，以在截面上彼此分离; 以及通过在所述漂移层的前表面上形成第二导电类型层，形成沟道层，所述第二导电类型层包括各个凹槽中每个电场弛豫层的前表面。

公开(公告)号：US20140339569A1

公开(公告)日：2014-11-20

申请号：US14262121

申请日：2014-04-25

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Masahiro SUGIMOTO ,  Yuichi TAKEUCHI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608

Abstract: A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a some layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer.

Abstract translation: 形成在具有设置有电极的前表面的碳化硅衬底上的半导体器件和设置有电极的背面包括漏极层，漂移层，基极层，位于 从前表面延伸到漂移层中并由绝缘膜，一些层，设置在漂移层和基底层之间的掩埋层绝缘的沟槽，其形成为从前表面到 其漂移层侧的端部大于从沟槽的前表面到远端的深度;以及第一外延层，其设置在掩埋层和基底层之间，并且具有比 埋层。