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    Computer hardware instruction and method for computing population counts
    11.
    发明授权
    Computer hardware instruction and method for computing population counts 失效
    用于计算人口数量的计算机硬件指令和方法

    公开(公告)号：US5717616A

    公开(公告)日：1998-02-10

    申请号：US19720

    申请日：1993-02-19

    申请人： Dale C. Morris

    发明人： Dale C. Morris

    IPC分类号： G06F7/50 ,  G06F7/60 ,  G06F17/00

    CPC分类号： G06F7/607

    摘要： An apparatus and method for computing population counts of large bit strings. The present invention utilizes carry-save adders to reduce the time required to perform a population count on an operand in a register. Because carry-save adders do not propagate carries they are inherently faster than full adders utilized in the prior art. Additionally, the present invention implements a novel method for computing population counts whereby the operand bit string is split into smaller blocks and multiple partial population counts are performed. These smaller partial population counts require less time to compute than a full population count over the entire operand bit string.

    摘要翻译： 一种用于计算大位串的总体计数的装置和方法。 本发明利用进位保存加法器来减少对寄存器中的操作数执行群体计数所需的时间。 由于携带保存加法器不传播传输，因此它们本身比现有技术中使用的全加器更快。 此外，本发明实现了一种用于计算总体计数的新方法，由此操作数位串被分割成更小的块，并且执行多个部分群计数。 与整个操作数位串的完整数量计数相比，这些较小的部分总数计算所需的计算时间较少。

    Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory
    15.
    发明授权
    Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory 失效
    选择性地强制执行CPU和共享内存之间的存储和加载操作的计算机

    公开(公告)号：US6079012A

    公开(公告)日：2000-06-20

    申请号：US968923

    申请日：1997-11-06

    申请人： Dale C. Morris ,  Bernard L. Stumpf ,  Barry J. Flahive ,  Jeffrey D. Kurtze ,  Stephen G. Burger ,  Ruby B. L. Lee ,  William R. Bryg

    发明人： Dale C. Morris ,  Bernard L. Stumpf ,  Barry J. Flahive ,  Jeffrey D. Kurtze ,  Stephen G. Burger ,  Ruby B. L. Lee ,  William R. Bryg

    IPC分类号： G06F15/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177 ,  G06F15/163

    CPC分类号： G06F9/52 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/522

    摘要： A computer apparatus which detects a store or load operation into or from a shared memory page by a program that does not provide for synchronization when executed by a CPU that completes instructions out of program order. After the store or load is detected, the CPU explicitly orders operations into the shared memory page. Store operations are ordered such that no new store into the shared memory page is performed until all prior store operations into the shared memory page are complete. Also, load operations are ordered such that load operations from the shared memory page are performed in program order. This ordering is achieved by maintaining a process bit and a memory attribute bit associated with a shared memory page. When both bits are true, all load or store operations referencing the shared memory page are ordered.

    摘要翻译： 一种计算机装置，其通过程序执行存储或加载操作，所述程序在由程序顺序完成指令的CPU执行时不提供同步。 检测到存储或加载后，CPU会将操作明确地命令到共享内存页面中。 存储操作被排序，使得在共享存储器页面中的所有先前的存储操作完成之前，不执行在共享存储器页面中的新存储。 此外，加载操作被排序，使得来自共享存储器页面的加载操作以程序顺序执行。 该排序通过维护与共享存储器页相关联的进程位和存储器属性位来实现。 当两个位都为真时，将对所有引用共享存储器页面的加载或存储操作进行排序。

    System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
    16.
    发明授权
    System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers 失效
    用于通过具有对应于多个寄存器的至少一个位的掩码恢复谓词寄存器的系统

    公开(公告)号：US5859999A

    公开(公告)日：1999-01-12

    申请号：US725573

    申请日：1996-10-03

    申请人： Dale C. Morris ,  Jack D. Mills

    发明人： Dale C. Morris ,  Jack D. Mills

    IPC分类号： G06F9/32 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/312

    CPC分类号： G06F9/3842 ,  G06F9/30072

    摘要： The present invention provides a method and apparatus for restoring a predicate register set. One embodiment of the invention includes decoding a first instruction which specifies a restoring operation to be performed on a predicate register set. In response to the first instruction, a mask is used to select a plurality of the predicate registers that are to be restored. The mask of the present invention consists of a first set of bits, with each bit of the first set of bits corresponding to a register in the predicate register set. When a bit of the first set of bits is set to one, the predicate register corresponding to that bit is restored. In one embodiment, the mask further includes one bit corresponding to a plurality of registers in the predicate register set, wherein when that bit is set to one, the plurality of registers corresponding to that bit are restored.

    摘要翻译： 本发明提供一种用于恢复谓词寄存器组的方法和装置。 本发明的一个实施例包括对指定要在谓词寄存器集上执行的恢复操作的第一指令进行解码。 响应于第一条指令，使用掩码来选择要恢复的多个谓词寄存器。 本发明的掩模由第一组位组成，其中第一组位的每个位对应于谓词寄存器组中的寄存器。 当第一组位的位被设置为1时，对应于该位的谓词寄存器被恢复。 在一个实施例中，掩码还包括对应于谓词寄存器集合中的多个寄存器的一个位，其中当该位被设置为1时，与该位相对应的多个寄存器被恢复。

    CABLE HARNESS SWITCHES
    19.
    发明申请
    CABLE HARNESS SWITCHES 审中-公开
    电缆线束开关

    公开(公告)号：US20130318271A1

    公开(公告)日：2013-11-28

    申请号：US13977912

    申请日：2011-01-31

    申请人： Michael Schlansker ,  Michael Renne Ty Tan ,  Nathan Lorenzo Binkert ,  Dale C. Morris ,  Wayne V. Sorin

    发明人： Michael Schlansker ,  Michael Renne Ty Tan ,  Nathan Lorenzo Binkert ,  Dale C. Morris ,  Wayne V. Sorin

    IPC分类号： G06F13/40

    CPC分类号： G06F13/40 ,  H04L49/40 ,  H04L49/60

    摘要： In one implementation, a cable harness switch includes a plurality of input ports, a first plurality of output ports, a second plurality of input ports, and a circuit switch module. Each input port from the plurality of input ports is configured to be coupled to a network link. Each output port from the first plurality of output ports is configured to be coupled to a network link. Each output port from the second plurality of output ports configured to be coupled to a network switch device. The circuit switch module is operatively coupled to the plurality of input ports, the first plurality of output ports, and the second plurality of output ports to define a network circuit including an input port from the plurality of input ports and an output port from the first plurality of output ports and the second plurality of output ports.

    摘要翻译： 在一个实施方式中，电缆束开关包括多个输入端口，第一多个输出端口，第二多个输入端口和电路开关模块。 来自多个输入端口的每个输入端口被配置为耦合到网络链路。 来自第一多个输出端口的每个输出端口被配置为耦合到网络链路。 来自第二多个输出端口的每个输出端口被配置为耦合到网络交换设备。 电路开关模块可操作地耦合到多个输入端口，第一多个输出端口和第二多个输出端口，以限定包括来自多个输入端口的输入端口的网络电路和来自第一 多个输出端口和第二多个输出端口。

    COMPUTER WORKLOAD MIGRATION
    20.
    发明申请
    COMPUTER WORKLOAD MIGRATION 有权
    计算机工作移动

    公开(公告)号：US20120054766A1

    公开(公告)日：2012-03-01

    申请号：US12870835

    申请日：2010-08-29

    申请人： Christophe de Dinechin ,  Dale C. Morris ,  Patrick Knebel ,  Russ W. Herrell

    发明人： Christophe de Dinechin ,  Dale C. Morris ,  Patrick Knebel ,  Russ W. Herrell

    IPC分类号： G06F9/46

    CPC分类号： G06F9/5088

    摘要： An event calling for a migration of a workload from a source processor set of processing units to a target processor set of processing units is detected. Processes of the workload are allocated to a second processor set of processing units so that some workload processes are executed on the source processor set and some workload processes are executed on a second processor set of processor units. Then, some workload processes are allocated to the second processor set so that no workload process is executing on the source processor set and at least some of said processes are executing on the second process set. The second processor set can be the target processor set or an intermediate processor set from which the workload is migrated to the target processor set.

    摘要翻译： 检测到要求将工作负载从源处理器集合处理单元迁移到处理单元集合的事件。 工作负载的处理被分配给处理单元的第二处理器集合，使得在源处理器集上执行一些工作负载过程，并且在第二处理器单元集合上执行一些工作负载过程。 然后，一些工作负载过程被分配给第二处理器集，使得在源处理器集上不执行工作负载过程，并且至少一些所述进程在第二进程集上执行。 第二处理器集合可以是目标处理器集合或中间处理器集合，工作负载从该集中迁移到目标处理器集合。