公开(公告)号：US5278985A

公开(公告)日：1994-01-11

申请号：US606711

申请日：1990-10-31

申请人： Daryl K. Odnert ,  Michael J. Mahon ,  Dale C. Morris ,  Jerome C. Huck ,  Ruby B. Lee ,  Stephen G. Burger ,  William R. Bryg ,  Vivek S. Pendharkar

发明人： Daryl K. Odnert ,  Michael J. Mahon ,  Dale C. Morris ,  Jerome C. Huck ,  Ruby B. Lee ,  Stephen G. Burger ,  William R. Bryg ,  Vivek S. Pendharkar

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3865

摘要： A method for operating a digital computer in response to the occurrence of an exception is disclosed. The method provides for the examination both of the contents of a predetermined computer location and of the instruction code for the instruction causing the exception. The computer then utilizes the result of those examinations to determine the dismissibility of the exception. The computer transfers control to the next instruction after the instruction which caused the exception if that instruction is dismissible.

摘要翻译： 公开了一种响应于异常发生而操作数字计算机的方法。 该方法提供检查预定计算机位置的内容和引起异常的指令的指令代码。 然后，计算机利用这些检查的结果来确定异常的可解除性。 如果该指令被忽略，则计算机将控制转移到导致异常的指令之后的下一个指令。

公开(公告)号：US4809160A

公开(公告)日：1989-02-28

申请号：US792702

申请日：1985-10-28

申请人： Michael J. Mahon ,  Allen Baum ,  William R. Bryg ,  Terrence C. Miller

发明人： Michael J. Mahon ,  Allen Baum ,  William R. Bryg ,  Terrence C. Miller

IPC分类号： G06F12/14 ,  G06F9/455 ,  G06F9/46 ,  G06F11/00 ,  G06F21/24

CPC分类号： G06F9/468 ,  G06F9/45537

摘要： A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.

摘要翻译： 提供了一种低开销方式，用于确保仅有足够权限的例程可以在分层计算机系统中的存储器的安全页面上执行，并且以有序和安全的方式提高低特权过程的特权级别。 这通过执行站在诸如用户程序的较低特权例程的过程调用与操作系统本身之间的单个“网关”分支指令来完成。

公开(公告)号：US4329685A

公开(公告)日：1982-05-11

申请号：US158052

申请日：1980-06-09

申请人： Michael J. Mahon ,  Roy R. Shanks

发明人： Michael J. Mahon ,  Roy R. Shanks

IPC分类号： G11C5/14 ,  G11C29/00 ,  H04Q9/00 ,  G11C17/00

CPC分类号： G11C29/78 ,  G11C29/006 ,  G11C29/832 ,  G11C5/14

摘要： This disclosure relates to a controlled selective power disconnect means for employment with the various circuits implemented on a crystalline wafer so that a particular circuit can be selectively disconnected when it has developed a defect or short or is unwanted in the system for other reasons. The disconnect means employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be melted or blown by a power disconnect signal thereby opening the gate. An amorphous switch can also be used such that networks can expand or contract around defective chips as required by the particular task or tasks involved.

摘要翻译： 本公开涉及一种受控的选择性电源断开装置，用于使用在晶体晶片上实施的各种电路，使得当其由于其它原因在系统中出现缺陷或缺陷或不需要时可以选择性地断开特定电路。 断开装置在电源和电路之间采用栅极，该栅极由可由电源断开信号熔化或熔断的保险丝控制，从而打开门。 还可以使用非晶开关，使得网络可以根据所涉及的特定任务或任务的要求在缺陷芯片周围扩展或收缩。

公开(公告)号：US06950135B2

公开(公告)日：2005-09-27

申请号：US09768477

申请日：2001-01-24

申请人： Bret A. McKee ,  Blaine D. Gaither ,  Michael J Mahon

发明人： Bret A. McKee ,  Blaine D. Gaither ,  Michael J Mahon

IPC分类号： G01S17/10 ,  G01S17/89 ,  G03B13/18 ,  G06K9/00 ,  H01L27/00 ,  H04N3/14 ,  H04N5/225 ,  H04N5/353 ,  H04N13/00 ,  H04N5/335

CPC分类号： G01S17/89 ,  G01S17/107

摘要： A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

摘要翻译： 包括能够测量图像拍摄装置和成像对象之间的距离的电路的数字图像捕获装置允许捕获面向图像捕获装置的对象的表面的三维数据。 距离数据通过添加闪光单元获得，并且对于图像捕获设备内的多个像素进行非常高分辨率的定时器来测量闪光从物体反射所需的时间。 由于光速恒定，所以可以从闪光灯到达设备的延迟来计算从闪光到物体到摄像装置的距离。 可以使用多个像素来构建面向图像捕获装置的物体的表面的三维模型。 可以采用包括距离数据的多个图像，以便生成对象表面的完整的三维模型。

公开(公告)号：US5757377A

公开(公告)日：1998-05-26

申请号：US650197

申请日：1996-05-20

申请人： Ruby Bei-Loh Lee ,  Michael J. Mahon

发明人： Ruby Bei-Loh Lee ,  Michael J. Mahon

IPC分类号： G06F7/544 ,  G06G7/30

CPC分类号： G06F7/5443

摘要： Circuitry combines a first operand A.sub.0, a second operand A.sub.1, and a third operand X in a blend function to produce a result Z. The result Z has a value equal to X*A.sub.0 +(1-X)* A.sub.1. The circuitry includes a plurality of logic gates organized in rows. When performing the blend operation each logic gates selects either a bit of the first operand A.sub.0 or a bit of the second operand A.sub.1. The selection for each logic gate depends upon bits of the third operand X. More specifically, each of the plurality of rows of logic gates selects the first operand A.sub.0 as output when an associated bit of the third operand X is at logic 1, and selects the second operand A.sub.1 as output when the associated bit of the third operand X is at logic 0. In addition to output generated by the plurality of rows of logic gates, a correction term is generated. For the blend operation, the correction term generated is the second operand A.sub.1. Partial product circuitry sums outputs of each row of logic gates and the correction term, to produce the result Z, so that the result Z has a value equal to X*A.sub.0 +(1-X)*A.sub.1.

摘要翻译： 电路在混合函数中组合第一操作数A0，第二操作数A1和第三操作数X以产生结果Z.结果Z具有等于X * A0 +（1-X）* A1的值。 电路包括以行组织的多个逻辑门。 当执行混合操作时，每个逻辑门选择第一操作数A0的位或第二操作数A1的位。 每个逻辑门的选择取决于第三操作数X的位。更具体地，当第三操作数X的相关位处于逻辑1时，多行逻辑门中的每一行选择第一操作数A0作为输出，并且选择 当第三操作数X的相关位为逻辑0时，第二操作数A1作为输出。除了由多行逻辑门产生的输出之外，还产生校正项。 对于混合操作，生成的校正项是第二操作数A1。 部分乘积电路对每行逻辑门和校正项的输出求和，以产生结果Z，使得结果Z具有等于X * A0 +（1-X）* A1的值。

公开(公告)号：US4947364A

公开(公告)日：1990-08-07

申请号：US392177

申请日：1989-08-09

申请人： Michael J. Mahon ,  Allen Baum

发明人： Michael J. Mahon ,  Allen Baum

IPC分类号： G06F7/52

CPC分类号： G06F7/5332

摘要： In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit. Second, for every other bit in the current section that is a "1", a shift-and-add operation is performed by shifting, via the preshifter, the contents of the first register by an amount equal to the number of bit places the bit is to the left of the low order bit of the current section and by adding, via the arithmetic logic unit, the preshifted contents of the first register to the contents of the second register. Third, for every section from the plurality of sections that does not contain low order bits of the first multiplicand, the contents of the first register "n" bits are shifted to the left.

摘要翻译： 在计算系统中，呈现执行第一被乘数和第二被乘数相乘的方法。 计算系统包括多个寄存器，指令解码器，算术逻辑单元和预定机。 第一被乘数被分成多个等长的部分。 每个部分包括“n”位，其中“n”是大于1的整数。 第二被乘数被放置在来自多个寄存器的第一寄存器中。 来自多个寄存器的第二寄存器被清零。 对于来自多个部分的每个部分，从包含第一乘法的高阶位的第一部分开始，并且进行到包含第一被乘数的低阶位的第一被乘数的最后部分以及以下三个子步骤。 首先，当当前部分的低位位为“1”时，第一寄存器的内容经由算术逻辑单元被添加到第二寄存器的内容。 第二，对于当前部分中的“1”的每个其他位，移位和加法运算是通过预定机器将第一寄存器的内容移位等于位置数 位位于当前部分的低位位置的左侧，并且经由算术逻辑单元将第一寄存器的预定内容相加到第二寄存器的内容。 第三，对于不包含第一被乘数的低位的多个部分的每个部分，第一个寄存器“n”位的内容向左移位。

公开(公告)号：US4777589A

公开(公告)日：1988-10-11

申请号：US750578

申请日：1985-06-28

申请人： Steven C. Boettner ,  William R. Bryg ,  David V. James ,  Tso-Kai Liu ,  Michael J. Mahon ,  Terrence C. Miller ,  William S. Worley, Jr.

发明人： Steven C. Boettner ,  William R. Bryg ,  David V. James ,  Tso-Kai Liu ,  Michael J. Mahon ,  Terrence C. Miller ,  William S. Worley, Jr.

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F12/14 ,  G06F12/08

CPC分类号： G06F12/1475 ,  G06F12/0292 ,  G06F12/0653 ,  G06F2212/206

摘要： A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

公开(公告)号：US4763242A

公开(公告)日：1988-08-09

申请号：US790570

申请日：1985-10-23

申请人： Ruby B. Lee ,  Michael J. Mahon

发明人： Ruby B. Lee ,  Michael J. Mahon

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F15/16 ,  G06F15/177 ,  G06F9/00

CPC分类号： G06F9/30181 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3897

摘要： A computer and an instruction set are presented which allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although an assist's operation and design need not be defined at the computer's date of design. Instructions are mapped to a particular assist. Assist instructions can be either executed in hardware by an assist, or emulated in software via a trap.

摘要翻译： 提出了一种计算机和指令集，其允许许多辅助被容易地并入到计算机中，并且允许指令集的扩展。 该计算机旨在支持在辅助和位置之间移动数据的指令，尽管协助的操作和设计不需要在计算机的设计日期进行定义。 指令映射到特定的辅助。 辅助指令可以通过辅助进行硬件执行，也可以通过陷阱在软件中进行仿真。

公开(公告)号：US4928239A

公开(公告)日：1990-05-22

申请号：US358460

申请日：1989-05-26

申请人： Allen Baum ,  William R. Bryg ,  Michael J. Mahon ,  Ruby B. Lee ,  Steven S. Muchnick

发明人： Allen Baum ,  William R. Bryg ,  Michael J. Mahon ,  Ruby B. Lee ,  Steven S. Muchnick

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F9/3824 ,  G06F12/0862 ,  G06F12/127 ,  G06F12/126 ,  G06F2212/6028

摘要： An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache.

摘要翻译： 向缓存提供指令; 该指令包括一个高速缓存控制说明符，用于标识被请求的数据类型。 基于高速缓存控制说明符，选择多个替换方案之一用于将高速缓存中的数据块交换。

公开(公告)号：US4354217A

公开(公告)日：1982-10-12

申请号：US166477

申请日：1980-07-07

申请人： Michael J. Mahon

发明人： Michael J. Mahon

IPC分类号： G06F11/20 ,  H01L23/525 ,  H02H5/04

CPC分类号： G06F11/2015 ,  H01L23/5256 ,  H01L2924/0002

摘要： This disclosure relates to a wafer scale power interconnect system by which defective circuits on the wafer can be automatically disconnected from the power and ground lines supplied to each of the circuits. The disconnect device employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be destroyed by an excessive current thereby opening the gate. The disconnect device may also be just such a fuse or a current limiter.

摘要翻译： 本公开涉及一种晶片级功率互连系统，通过该晶片级功率互连系统，晶片上的故障电路可以自动地从提供给每个电路的电源线和地线断开。 断开装置在电源和电路之间使用栅极，该栅极由可被过大电流破坏的熔丝控制，从而打开栅极。 断开装置也可以仅仅是这种保险丝或电流限制器。