公开(公告)号：US06465857B1

公开(公告)日：2002-10-15

申请号：US09593332

申请日：2000-06-14

申请人： Davide Patti ,  Giuseppina Valvo

发明人： Davide Patti ,  Giuseppina Valvo

IPC分类号： H01L31115

CPC分类号： H01L31/115

摘要： A chip of semiconductor material includes a first layer with a first type of conductivity having a surface on the first major surface of the chip, a second layer with the first type of conductivity having a surface on the second major surface of the chip, and a third layer with the first type of conductivity having a resistivity lower than those of the first and second layers and disposed between the first layer and the second layer. A first region with a second, type of conductivity, extends from the first surface into the first layer, and a second region with the second type of conductivity, extends from the second major surface into the second layer. First, second and third electrical connections are provided for connection with the first region, the second region, and the third layer, respectively. To provide a position detector which does not require a large number of connections, the second electrical connection includes two electrodes arranged a predetermined distance apart on the surface of the second region.

摘要翻译： 半导体材料芯片包括具有第一导电类型的第一层，其具有在芯片的第一主表面上的表面，具有第一类型导电性的第二层具有在芯片的第二主表面上的表面，以及 第三层，其第一类型的导电性具有比第一和第二层的电阻率低的电阻率，并且设置在第一层和第二层之间。 具有第二导电类型的第一区域从第一表面延伸到第一层，并且具有第二类型导电性的第二区域从第二主表面延伸到第二层。 首先，分别提供第二和第三电连接用于与第一区域，第二区域和第三层连接。 为了提供不需要大量连接的位置检测器，第二电连接包括在第二区域的表面上隔开预定距离布置的两个电极。

公开(公告)号：US06362025B1

公开(公告)日：2002-03-26

申请号：US09441575

申请日：1999-11-17

申请人： Davide Patti ,  Angelo Pinto

发明人： Davide Patti ,  Angelo Pinto

IPC分类号： H01L21332

CPC分类号： H01L29/66666 ,  H01L21/76221 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/7827

摘要： A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions. The method further includes forming a dielectric coating on the lateral surface of the trench, depositing electrically-conductive material in the trench in contact with the dielectric, and forming elements for electrical contact with the n conductivity layer, with the second region, and with the electrically-conductive material inside the trench, to produce drain, source and gate electrodes of the MOSFET, respectively.

摘要翻译： 通过与DPSA技术相兼容的方法生产高质量和重复性的亚微米垂直沟道MOSFET。 方法步骤在具有n导电性层的半导体材料的晶片上进行。 首先，将n种杂质离子和p杂质离子注入到该层的区域中，并对晶片进行高温处理。 杂质，注入剂量和能量以及高温处理时间和温度等于形成第一p区，以及与第一区形成pn结的第二n区。 挖沟的沟槽与第一区域和第二区域相交。 该方法还包括在沟槽的侧表面上形成电介质涂层，在与电介质接触的沟槽中沉积导电材料，以及形成用于与第n个导电层与第二区域电接触的元件，以及与 沟槽内的导电材料，分别产生MOSFET的漏极，源极和栅极。

公开(公告)号：US07528461B2

公开(公告)日：2009-05-05

申请号：US11423335

申请日：2006-06-09

申请人： Davide Patti ,  Sebastiano Aparo

发明人： Davide Patti ,  Sebastiano Aparo

IPC分类号： H01L29/73

CPC分类号： H01L29/7302 ,  H01L29/0692 ,  H01L29/866

摘要： A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate. An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

摘要翻译： 双极功率晶体管不包括电连接在基极和集电极之间的齐纳二极管的集成，以限制集电​​极电压。 功率晶体管形成在衬底中，并且包括沿衬底的周边形成P-N结的均衡扩散和辅助扩散。 均衡传导层与用于电短路P-N结的均衡扩散和辅助扩散接触。

公开(公告)号：US20070013032A1

公开(公告)日：2007-01-18

申请号：US11423335

申请日：2006-06-09

申请人： Davide Patti ,  Sebastiano Aparo

发明人： Davide Patti ,  Sebastiano Aparo

IPC分类号： H01L27/082

CPC分类号： H01L29/7302 ,  H01L29/0692 ,  H01L29/866

摘要： A bipolar power transistor does not include integration of a Zener diode electrically connected between the base and collector for limiting the collector voltage. The power transistor is formed in a substrate, and includes an equalization diffusion and an auxiliary diffusion forming a P-N junction along a perimeter of the substrate An equalization conduction layer is in contact with the equalization diffusion and the auxiliary diffusion for electrically shorting the P-N junction.

摘要翻译： 双极功率晶体管不包括电连接在基极和集电极之间的齐纳二极管的集成，以限制集电​​极电压。 功率晶体管形成在衬底中，并且包括沿着衬底的周边形成P-N结的均衡扩散和辅助扩散。均衡传导层与用于电短路P-N结的均衡扩散和辅助扩散接触。

公开(公告)号：US07126167B2

公开(公告)日：2006-10-24

申请号：US10888789

申请日：2004-07-09

申请人： Davide Patti ,  Antonino Torres

发明人： Davide Patti ,  Antonino Torres

IPC分类号： H01L29/43

CPC分类号： H01L29/7395

摘要： A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.

摘要翻译： 一种集成在由第一导电类型的半导体衬底中的第一导电类型的半导体层的器件，其包括电压控制电阻结构和IGBT器件的第二导电类型的半导体层，其中所述电阻结构包括至少一个第一 围绕半导体层的一部分的导电性的类型。

公开(公告)号：US06815798B2

公开(公告)日：2004-11-09

申请号：US10439277

申请日：2003-05-15

申请人： Natale Aiello ,  Davide Patti

发明人： Natale Aiello ,  Davide Patti

IPC分类号： H01L2900

CPC分类号： H01L27/0676 ,  H01L29/94

摘要： A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

公开(公告)号：US07675135B2

公开(公告)日：2010-03-09

申请号：US11575227

申请日：2005-09-12

申请人： Davide Patti ,  Giuditta Settanni

发明人： Davide Patti ,  Giuditta Settanni

IPC分类号： H01L23/58

CPC分类号： H01L29/0615

摘要： Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (α) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

摘要翻译： 可以有效地防止在必须实现集成装置的主结（P_tub 1，（P_tub2，...））的周边高压环延伸注入区域（RHV）的中断时产生的不稳定性和相关缺点，这一重要结果 通过非常简单的方法实现：每当必须产生高压环延伸的中断（I）时，沿着与周边注入区域的共同正交方向在其上没有实现直线，相反，窄的中断是 倾斜或倾斜地定位在周边高压环延伸的宽度上，在直线中断的情况下，倾斜角（α）通常可以在30度和60度之间，更优选地在45度或更接近于它。 ，当实现周边高压环延伸区域时，通过将其从掺杂剂注入掩蔽来产生窄中断。

公开(公告)号：US20080237773A1

公开(公告)日：2008-10-02

申请号：US11575227

申请日：2005-09-12

申请人： Davide Patti ,  Giuditta Settanni

发明人： Davide Patti ,  Giuditta Settanni

IPC分类号： H01L21/265 ,  H01L29/36

CPC分类号： H01L29/0615

摘要： Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (α) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

摘要翻译： 可以有效地防止在必须实现集成装置的主结（P_tub 1，（P_tub 2，...）的周边高压环延伸注入区域（RHV）的中断时产生的不稳定性和相关缺点，这很重要 结果是通过非常简单的方法实现的：每当必须产生高压环延伸的中断（I）时，沿着与周边注入区域的共同正交方向在其上没有实现直线，相反，窄中断 在圆周高压环延伸部的宽度上倾斜或倾斜地定义，在直线中断的情况下，倾斜角（α）通常可以包含30度到60度之间，更优选地在45度附近。 当然，当实现周边高电压环延伸区域时，通过将其从掺杂剂注入掩蔽来产生窄的中断。

公开(公告)号：US06774061B2

公开(公告)日：2004-08-10

申请号：US09811159

申请日：2001-03-15

申请人： Salvatore Coffa ,  Davide Patti

发明人： Salvatore Coffa ,  Davide Patti

IPC分类号： H01L21336

CPC分类号： H01L21/28273 ,  Y10S438/962

摘要： A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

摘要翻译： 公开了一种在氧化物层中形成硅纳米晶体薄层的工艺。 该方法包括在半导体衬底上将衬底的第一部分热氧化成氧化物层，在氧化物层内形成硅离子，以及热处理硅离子以成为硅纳米晶体的薄层。 在本发明的方法中，硅离子的形成是通过以0.1keV至7keV，优选1至5keV之间的离子化能量将硅离子离子注入氧化物中。 这允许硅原子在比其他可能的温度更低的温度下聚结。 另外，可以通过在多于一个能级执行多于一次的注入来形成多于一层的纳米晶体。 本发明的实施例可用于形成具有非常小尺寸的非常高质量的非易失性存储器件。

公开(公告)号：US06590272B2

公开(公告)日：2003-07-08

申请号：US09991555

申请日：2001-11-21

申请人： Davide Patti

发明人： Davide Patti

IPC分类号： H01L2900

CPC分类号： H01L28/20 ,  H01L27/0802 ,  H01L29/8605

摘要： A structure for a semiconductor resistive element, applicable in particular to power components, having a high concentration substrate of the n type, a first epitaxial layer of the n type, a region of the p type arranged on said first epitaxial layer so to form the resistive element proper, a second epitaxial layer of n type grown on said first epitaxial layer to make the region of the p type a buried region, and an additional layer of the n type with a higher concentration with respect to the second epitaxial level, positioned on the embedded region. Low resistivity regions of the p type adapted to make low resistivity deep contacts for the resistor are provided. The buried region can be made either with a development that is substantially uniform in its main direction of extension or so to present, at on part of its length, a structure of adjacent subregions in marginal continuity. In this way, either a resistive element presenting a substantially linear performance in all ranges of applied voltage or a resistive element presenting a marked increase of the resistance value as the applied voltage increases can be made. This all with the additional possibility of selectively varying the resistance value demonstrated before the increase.

摘要翻译： 一种用于半导体电阻元件的结构，特别适用于具有n型高浓度衬底，n型第一外延层，布置在所述第一外延层上的p型区域的功率元件，从而形成 电阻元件本体，在所述第一外延层上生长以使p型区域成为掩埋区域的n型第二外延层和相对于第二外延级别具有较高浓度的n型附加层，定位 在嵌入式区域。 提供适于为电阻器制造低电阻率深触点的p型低电阻率区域。 掩埋区域可以通过在其主要延伸方向上基本均匀的发展来实现，或者在其长度的一部分上呈现边缘连续性的相邻子区域的结构。 以这种方式，可以在所施加的电压的所有范围内呈现基本上线性的电阻元件，或者施加的电压增加时呈现电阻值的显着增加的电阻元件。 这一切都具有选择性地改变在增加之前显示的电阻值的附加可能性。