公开(公告)号：US06465857B1

公开(公告)日：2002-10-15

申请号：US09593332

申请日：2000-06-14

申请人： Davide Patti ,  Giuseppina Valvo

发明人： Davide Patti ,  Giuseppina Valvo

IPC分类号： H01L31115

CPC分类号： H01L31/115

摘要： A chip of semiconductor material includes a first layer with a first type of conductivity having a surface on the first major surface of the chip, a second layer with the first type of conductivity having a surface on the second major surface of the chip, and a third layer with the first type of conductivity having a resistivity lower than those of the first and second layers and disposed between the first layer and the second layer. A first region with a second, type of conductivity, extends from the first surface into the first layer, and a second region with the second type of conductivity, extends from the second major surface into the second layer. First, second and third electrical connections are provided for connection with the first region, the second region, and the third layer, respectively. To provide a position detector which does not require a large number of connections, the second electrical connection includes two electrodes arranged a predetermined distance apart on the surface of the second region.

摘要翻译： 半导体材料芯片包括具有第一导电类型的第一层，其具有在芯片的第一主表面上的表面，具有第一类型导电性的第二层具有在芯片的第二主表面上的表面，以及 第三层，其第一类型的导电性具有比第一和第二层的电阻率低的电阻率，并且设置在第一层和第二层之间。 具有第二导电类型的第一区域从第一表面延伸到第一层，并且具有第二类型导电性的第二区域从第二主表面延伸到第二层。 首先，分别提供第二和第三电连接用于与第一区域，第二区域和第三层连接。 为了提供不需要大量连接的位置检测器，第二电连接包括在第二区域的表面上隔开预定距离布置的两个电极。

公开(公告)号：US06441445B1

公开(公告)日：2002-08-27

申请号：US09413740

申请日：1999-10-06

申请人： Salvatore Leonardi ,  Davide Patti ,  Delfo Sanfilippo

发明人： Salvatore Leonardi ,  Davide Patti ,  Delfo Sanfilippo

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L21/823462

摘要： The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.

摘要翻译： 集成电路器件具有垂直导电结构，其中包含双极晶体管的基极的区域具有不同浓度的区域。 在电荷流动更强烈和其他地方较高的地方，浓度较低。 因此获得双极晶体管的高增益和电子开关在导通中的低电阻。

公开(公告)号：US06297118B1

公开(公告)日：2001-10-02

申请号：US09548784

申请日：2000-04-13

申请人： Davide Patti

发明人： Davide Patti

IPC分类号： H01L21331

CPC分类号： H01L29/66303 ,  H01L29/0804 ,  H01L29/7304

摘要： A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers. The emitter buried region and the sinker emitter region delimit in each emitter finger pairs of sections which are mutually spaced and delimit between one another a central region of the epitaxial layer. The sinker emitter region of each pair of sections of an emitter finger extend in the vicinity of mutually facing edges of the emitter buried region of the pair of sections.

摘要翻译： 一种晶体管，包括具有第一导电类型的外延层，具有第二导电类型的基极掩埋区域和具有第二导电类型的沉降片基极区域，从晶体管的主表面延伸到基底掩埋区域， 与基极掩埋区一起，发射极指在外延层中。 晶体管还包括具有第一导电类型的发射极掩埋区和高于外延层的掺杂水平的掺杂水平。 发射极掩埋区域在与基底掩埋区域相邻的位置嵌入在外延层中。 具有第一导电类型和掺杂水平的沉降弧发射极区域，其高于外延层的掺杂水平并且从发射极指状物内部的主表面延伸到发射极掩埋区域。 发射极掩埋区域和沉陷弧发射极区域在每个发射极指状物中限定，这些区域彼此间隔开并且在彼此之间限定外延层的中心区域。 发射极指的每对部分的沉降弧发射极区域在该对部分的发射极掩埋区域的相互面对的边缘附近延伸。

公开(公告)号：US05998855A

公开(公告)日：1999-12-07

申请号：US951686

申请日：1997-10-16

申请人： Davide Patti

发明人： Davide Patti

IPC分类号： H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00 ,  H01L31/11

CPC分类号： H01L29/66303 ,  H01L29/7304

摘要： A bipolar power transistor of interdigitated geometry having a buried P type base region, a buried N type emitter region, a P type base-contact region, an N type emitter-contact region, connected to an emitter electrode and an N type connection region disposed around the emitter-contact region. The emitter region is buried within the base region in such a way that the buried emitter region and the connection region delimit a P type screen region. The transistor further includes a biasing P type region in contact with the emitter electrode, which extends up to the screen region.

摘要翻译： 具有掩埋P型基极区域的埋入式几何形状的双极型功率晶体管，与发射电极连接的N型发射极区域，P型基极接触区域，N型发射极 - 接触区域和配置在N型连接区域中的N型发射极 - 围绕发射极 - 接触区域。 发射极区域以埋地发射极区域和连接区域限定P型屏幕区域的方式埋在基极区域内。 晶体管还包括与发射电极接触的偏置P型区域，其延伸到屏幕区域。

公开(公告)号：US08299579B2

公开(公告)日：2012-10-30

申请号：US13013513

申请日：2011-01-25

申请人： Davide Patti ,  Vincenzo Sciacca

发明人： Davide Patti ,  Vincenzo Sciacca

IPC分类号： H01L29/66

CPC分类号： H03K17/0828 ,  H03K17/567

摘要： An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.

摘要翻译： 集成功率晶体管包括发射极或源极区域以及将发射极或源极区域互连并限定至少一个连接焊盘的梳状图案化金属电极结构。 梳状图案化的金属电极结构包括多个手指。 电流感测电阻器产生代表由集成功率晶体管传送到负载的电流的电压降。 电流感测电阻器包括具有已知电阻值的电流携带金属轨道的一部分，并且在手指之一和沿着载流金属轨道的可连接点之间延伸。

公开(公告)号：US20050051813A1

公开(公告)日：2005-03-10

申请号：US10888789

申请日：2004-07-09

申请人： Davide Patti ,  Antonino Torres

发明人： Davide Patti ,  Antonino Torres

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L29/7395

摘要： A device integrated in a semiconductor substrate of a first type of conductivity being crowned by a semiconductor layer of a second type of conductivity comprising a voltage controlled resistive structure and an IGBT device, wherein the resistive structure comprises at least one substantially annular region of the first type of conductivity which surrounds a portion of the semiconductor layer.

摘要翻译： 一种集成在由第一导电类型的半导体衬底中的第一导电类型的半导体层的器件，其包括电压控制电阻结构和IGBT器件的第二导电类型的半导体层，其中所述电阻结构包括至少一个第一 围绕半导体层的一部分的导电性的类型。

公开(公告)号：US06696916B2

公开(公告)日：2004-02-24

申请号：US09746373

申请日：2000-12-22

申请人： Delfo Sanfilippo ,  Davide Patti

发明人： Delfo Sanfilippo ,  Davide Patti

IPC分类号： H01C1012

CPC分类号： H01L28/20 ,  H01C7/1013 ,  H01C17/075 ,  H01L27/0802

摘要： The high-voltage resistor is of the vertical type, and is formed in a chip which includes a high-voltage region and a low-voltage region superimposed on the high-voltage region, both having a first conductivity type. An isolation region, at least partially buried, extends between the high-voltage region and the low-voltage region, and delimits a vertical resistive region connecting the high-voltage region to the low-voltage region.

摘要翻译： 高压电阻器是垂直型的，并且形成在包括叠加在高电压区域上的高电压区域和低电压区域的芯片中，两者都具有第一导电类型。 至少部分埋置的隔离区域在高电压区域和低压区域之间延伸，并且限定将高电压区域连接到低电压区域的垂直电阻区域。

公开(公告)号：US06696741B1

公开(公告)日：2004-02-24

申请号：US09443742

申请日：1999-11-19

申请人： Cesare Ronsisvalle ,  Piero Giorgio Fallica ,  Davide Patti

发明人： Cesare Ronsisvalle ,  Piero Giorgio Fallica ,  Davide Patti

IPC分类号： H01L2358

CPC分类号： H01L29/7802 ,  H01L21/762 ,  H01L29/0653

摘要： PN junction structure including a first junction region of a first conductivity type, and a second junction region of a second conductivity type, wherein between said first and second junction regions a grid of buried insulating material regions is provided.

摘要翻译： PN结结构，其包括第一导电类型的第一结区域和第二导电类型的第二结区域，其中在所述第一和第二接合区域之间提供掩埋绝缘材料区域格栅。

公开(公告)号：US06362025B1

公开(公告)日：2002-03-26

申请号：US09441575

申请日：1999-11-17

申请人： Davide Patti ,  Angelo Pinto

发明人： Davide Patti ,  Angelo Pinto

IPC分类号： H01L21332

CPC分类号： H01L29/66666 ,  H01L21/76221 ,  H01L21/763 ,  H01L21/8249 ,  H01L29/7827

摘要： A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions. The method further includes forming a dielectric coating on the lateral surface of the trench, depositing electrically-conductive material in the trench in contact with the dielectric, and forming elements for electrical contact with the n conductivity layer, with the second region, and with the electrically-conductive material inside the trench, to produce drain, source and gate electrodes of the MOSFET, respectively.

摘要翻译： 通过与DPSA技术相兼容的方法生产高质量和重复性的亚微米垂直沟道MOSFET。 方法步骤在具有n导电性层的半导体材料的晶片上进行。 首先，将n种杂质离子和p杂质离子注入到该层的区域中，并对晶片进行高温处理。 杂质，注入剂量和能量以及高温处理时间和温度等于形成第一p区，以及与第一区形成pn结的第二n区。 挖沟的沟槽与第一区域和第二区域相交。 该方法还包括在沟槽的侧表面上形成电介质涂层，在与电介质接触的沟槽中沉积导电材料，以及形成用于与第n个导电层与第二区域电接触的元件，以及与 沟槽内的导电材料，分别产生MOSFET的漏极，源极和栅极。

公开(公告)号：US20110181323A1

公开(公告)日：2011-07-28

申请号：US13013513

申请日：2011-01-25

申请人： Davide Patti ,  Vincenzo Sciacca

发明人： Davide Patti ,  Vincenzo Sciacca

IPC分类号： H03K3/00 ,  H01L21/8222

CPC分类号： H03K17/0828 ,  H03K17/567

摘要： An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.

摘要翻译： 集成功率晶体管包括发射极或源极区域以及将发射极或源极区域互连并限定至少一个连接焊盘的梳状图案化金属电极结构。 梳状图案化的金属电极结构包括多个手指。 电流感测电阻器产生代表由集成功率晶体管传送到负载的电流的电压降。 电流感测电阻器包括具有已知电阻值的电流携带金属轨道的一部分，并且在手指之一和沿着载流金属轨道的可连接点之间延伸。