公开(公告)号：US07846321B2

公开(公告)日：2010-12-07

申请号：US11874766

申请日：2007-10-18

申请人： Steven Diamond ,  Ian Harding ,  Richard Williams

发明人： Steven Diamond ,  Ian Harding ,  Richard Williams

IPC分类号： C12Q1/00 ,  C12M1/00

CPC分类号： G01N27/3274

摘要： Measurement of the series track resistance of a working and counter electrode pair in an electrochemical test strip provide error detection for multiple variations in the quality of the test strip, as well as the operation of strip in the test meter. In particular, a single measurement of series resistance can be used to detect and generate an error message when an incorrect reading is likely to result due to (1) damaged electrode tracks, (2) fouled electrode surfaces, (3) dirty strip contacts, or (4) short circuit between the electrodes.

摘要翻译： 在电化学测试条中测量工作电极对和对电极对的串联轨道电阻可以提供测试条质量的多种变化的错误检测以及测试仪中条带的操作。 特别地，当由于（1）损坏的电极轨迹，（2）污染的电极表面，（3）脏的带状接触，或者（3））导致不正确的读数时，可以使用串联电阻的单次测量来检测并产生错误信息， 或（4）电极之间的短路。

公开(公告)号：US07837941B2

公开(公告)日：2010-11-23

申请号：US11279044

申请日：2006-04-07

申请人： Ian Harding ,  Sridhar G. Iyengar ,  Ha Nguyen ,  Richard Williams

发明人： Ian Harding ,  Sridhar G. Iyengar ,  Ha Nguyen ,  Richard Williams

IPC分类号： G01N33/49

CPC分类号： G01N27/26 ,  G01N33/4905 ,  G01N33/86

摘要： A device for measuring blood coagulation time is formed from a first substrate; a second substrate; a spacer layer disposed between the first and second substrates, said spacer layer having an opening formed therein defining a sample receiving chamber, a vented sink chamber, and an elongated reservoir forming a conduit for liquid movement between the sample receiving chamber and the sink chamber; a first electrode disposed on the first substrate, said first electrode being exposed in the reservoir portion through a first opening in the spacer layer; and a second electrode disposed on the second substrate, said second electrode being exposed in the reservoir portion through a second opening in the spacer layer. The device of the invention is used in combination with an apparatus that is connected to the first and second electrodes for measuring current flow between the first and second electrodes. Changes in observed current are indicative of flow through the device, and a cessation of flow indicates coagulation.

摘要翻译： 用于测量凝血时间的装置由第一基底形成; 第二基板; 间隔层，其设置在所述第一和第二基板之间，所述间隔层具有形成在其中的开口，所述隔离件限定了样品接收室，通气的宿室和形成用于液体在样品接收室和宿室之间移动的导管的细长储存器; 设置在所述第一基板上的第一电极，所述第一电极通过所述间隔层中的第一开口暴露在所述储存部分中; 以及设置在所述第二基板上的第二电极，所述第二电极通过所述间隔层中的第二开口暴露在所述储存部分中。 本发明的装置与连接到第一和第二电极的装置结合使用，用于测量第一和第二电极之间的电流。 观察到的电流的变化表示通过该装置的流动，并且停止流动表示凝结。

公开(公告)号：US07807993B2

公开(公告)日：2010-10-05

申请号：US11671877

申请日：2007-02-06

申请人： Beverley Anne Brown ,  Janos Veres ,  Remi Manouk Anemian ,  Richard Williams ,  Simon Dominic Ogier ,  Stephen William Leeming

发明人： Beverley Anne Brown ,  Janos Veres ,  Remi Manouk Anemian ,  Richard Williams ,  Simon Dominic Ogier ,  Stephen William Leeming

IPC分类号： H01L35/24

CPC分类号： C08L39/04 ,  C07F7/0805 ,  C07F7/081 ,  C08L35/06 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0052 ,  H01L51/0055 ,  H01L51/0056 ,  H01L51/0059 ,  H01L51/0071 ,  H01L51/0072 ,  H01L51/0073 ,  H01L51/0074 ,  H01L51/0094 ,  H01L51/0566 ,  H01L51/42 ,  H01L51/50 ,  Y02E10/549 ,  C08L2666/02 ,  C08L2666/28

摘要： A compound of formula 8 and uses thereof in various electronic devices and in a formulation for ink jet printing and in an organic semiconducting layer formulation.

摘要翻译： 式8的化合物及其在各种电子装置和用于喷墨印刷和有机半导体层制剂的制剂中的用途。

公开(公告)号：US07476329B2

公开(公告)日：2009-01-13

申请号：US11050191

申请日：2005-02-02

申请人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

发明人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

IPC分类号： H01L21/00

CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

摘要翻译： 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。 沉积在存储元件层上的第一导电层。 第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。 使用第一掩模层，蚀刻第一导电层。 沉积第二介电层，覆盖第一掩模层和电介质区域。 去除第二介电层的一部分以露出第一掩模层。 对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。 蚀刻暴露第一导电层。

公开(公告)号：US20080048287A1

公开(公告)日：2008-02-28

申请号：US11891006

申请日：2007-08-08

申请人： Richard Williams ,  Donald Disney ,  Wai Chan

发明人： Richard Williams ,  Donald Disney ,  Wai Chan

IPC分类号： H01L29/00 ,  H01L21/761

CPC分类号： H01L29/0646 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

公开(公告)号：US20080042232A1

公开(公告)日：2008-02-21

申请号：US11890993

申请日：2007-08-08

申请人： Richard Williams ,  Donald Disney ,  Wai Chan ,  Jun-Wei Chen ,  HyungSik Ryu

发明人： Richard Williams ,  Donald Disney ,  Wai Chan ,  Jun-Wei Chen ,  HyungSik Ryu

IPC分类号： H01L29/00 ,  H01L21/761

CPC分类号： H01L29/0646 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/763 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

摘要翻译： 用于半导体衬底的各种隔离结构包括形成在衬底中的沟槽，其填充有电介质材料或填充有导电材料并且沿着沟槽的壁衬有介电层。 沟槽可以与掺杂的侧壁隔离区域组合使用。 沟槽和侧壁隔离区域都可以是环形的并且包围衬底的隔离袋。 隔离结构通过不包括显着的热处理或掺杂剂扩散的模块化注入和蚀刻工艺形成，使得所得到的结构是紧凑的并且可以紧密地堆积在衬底的表面中。

公开(公告)号：US20080023762A1

公开(公告)日：2008-01-31

申请号：US11881942

申请日：2007-07-30

申请人： Richard Williams ,  Michael Cornell ,  Wai Chan

发明人： Richard Williams ,  Michael Cornell ,  Wai Chan

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/82285 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7835

摘要： A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

公开(公告)号：US20080017966A1

公开(公告)日：2008-01-24

申请号：US11696172

申请日：2007-04-03

申请人： Richard Williams ,  Allen Lam ,  Keng Lin

发明人： Richard Williams ,  Allen Lam ,  Keng Lin

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L23/02

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor product includes a die and leadframe included in a package made of plastic or other insulating material. The die and leadframe are dimensioned so that they overlap in at least one location. One or more pillar bumps, formed from as a cylindrical conductive base topped with a solder bump are used to interconnect the leadframe and die in the region of overlap. The pillar bumps perform several purposes including: electrical connection between the leadframe and die, support for the die during packaging and conduction of heat away from the die.

摘要翻译： 半导体产品包括包含在由塑料或其它绝缘材料制成的封装中的管芯和引线框架。 模具和引线框架的尺寸使其在至少一个位置重叠。 使用由作为圆顶状的导电基底形成的一个或多个柱状凸起，该基底顶部具有焊料凸点，以在重叠区域内互连引线框架和管芯。 支柱凸块执行若干目的，包括：引线框架和模具之间的电连接，在封装期间支撑模具并将热量从模具传导出去。

公开(公告)号：US20080009625A1

公开(公告)日：2008-01-10

申请号：US11822594

申请日：2007-07-09

申请人： Beverley Brown ,  Janos Veres ,  Remi Anemian ,  Richard Williams ,  Simon Ogier ,  Stephen Leeming

发明人： Beverley Brown ,  Janos Veres ,  Remi Anemian ,  Richard Williams ,  Simon Ogier ,  Stephen Leeming

IPC分类号： C07D401/10 ,  C07C50/22 ,  C07D409/10 ,  C07F7/08 ,  H01L51/30

CPC分类号： C08L39/04 ,  C07F7/0805 ,  C07F7/081 ,  C08L35/06 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0039 ,  H01L51/0052 ,  H01L51/0055 ,  H01L51/0056 ,  H01L51/0059 ,  H01L51/0071 ,  H01L51/0072 ,  H01L51/0073 ,  H01L51/0074 ,  H01L51/0094 ,  H01L51/0566 ,  H01L51/42 ,  H01L51/50 ,  Y02E10/549 ,  C08L2666/02 ,  C08L2666/28

摘要： An organic semiconducting layer formulation, which comprises: an organic binder which has a permittivity, ε, at 1,000 Hz of 3.3 or less; and a polyacene compound of Formula: (A) wherein: each of R1, R2, R3, R, R5, R6, R7, R8, R9, R10, R11, and R12, which may be the same or different, independently represents hydrogen; an optionally substituted C1-C40 carbyl or hydrocarbyl group; an optionally substituted C1-C40 alkoxy group; an optionally substituted C6-C40 aryloxy group; an optionally substituted C7-C40 alkylaryloxy group; an optionally substituted C2-C40 alkoxycarbonyl group; an optionally substituted C7-C40 aryloxycarbonyl group; a cyano group (—CN); a carbamoyl group (—C(═O)NH2); a haloformyl group (—C(═O)—X, wherein X represents a halogen atom); a formyl group (—C(═O)—H); an isocyano group; an isocyanate group; a thiocyanate group or a thioisocyanate group; an optionally substituted amino group; a hydroxy group; a nitro group; a CF3 group; a halo group (CI, Br, F); or an optionally substituted silyl group; and wherein independently each pair of R2 and R3 and/or R8 and R9, may be cross-bridged to form a C4-C40 saturated or unsaturated ring, which saturated or unsaturated ring may be intervened by an oxygen atom, a sulphur atom or a group shown by formula —N(Ra)— (wherein Ra is a hydrogen atom or an optionally substituted hydrocarbon group), or may optionally be substituted; and wherein one or more of the carbon atoms of the polyacene skeleton may optionally be substituted by a heteroatom selected from N, P, As, O, S, Se and Te; and wherein independently any two or more of the substituents R1—R12 which are located on adjacent ring positions of the polyacene may, together, optionally constitute a further C4-C40 saturated or unsaturated ring optionally interrupted by O, S or —N(Ra) where Ra is as defined above) or an aromatic ring system, fused to the polyacene; and wherein n is 0, 1, 2, 3 or 4, also claimed is an electronic device, particularly an organic field effect transistor comprising the organic semiconductor layer formulation.

公开(公告)号：US20070271113A1

公开(公告)日：2007-11-22

申请号：US11829028

申请日：2007-07-26

申请人： Dwayne Nelson ,  Richard Williams ,  Richard Rowe ,  Timothy Moser

发明人： Dwayne Nelson ,  Richard Williams ,  Richard Rowe ,  Timothy Moser

IPC分类号： G06Q50/00

CPC分类号： G07F17/3206 ,  G06Q30/02 ,  G06Q50/12 ,  G06Q50/34 ,  G07F17/32 ,  G07F17/3234 ,  G07F17/3237 ,  G07F17/3239 ,  G07F17/3255

摘要： Gaming establishment patrons may be categorized and responsive services and features presented whether or not the patrons (or their companions) are known. Gaming and non-gaming activities of a patron may be identified and tracked. Information from various private and/or public databases accessible by a gaming establishment, may be used for patron ranking and to determine offers, goods and services that may be targeted to a patron.

摘要翻译： 无论顾客（或其同伴）是否已知，游戏机构的顾客都可能被分类并提供响应性服务和功能。 赞助人的游戏和非游戏活动可能被识别和跟踪。 来自游戏机构可访问的各种私人和/或公共数据库的信息可用于顾客排名，并确定可能针对顾客的优惠，商品和服务。