公开(公告)号：US06331469B1

公开(公告)日：2001-12-18

申请号：US09684822

申请日：2000-10-10

申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

摘要翻译： 一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应 提供沟槽隔离方法。 在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。 在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。 在内壁氧化膜的表面上形成衬垫。 沟槽填充有电介质膜。 蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

公开(公告)号：US20050056888A1

公开(公告)日：2005-03-17

申请号：US10917026

申请日：2004-08-11

申请人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US06717231B2

公开(公告)日：2004-04-06

申请号：US10224017

申请日：2002-08-20

申请人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

发明人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来，在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

公开(公告)号：US06482715B2

公开(公告)日：2002-11-19

申请号：US09927340

申请日：2001-08-13

申请人： Tai-su Park ,  Ho-kyu Kang ,  Dong-ho Ahn ,  Moon-han Park

发明人： Tai-su Park ,  Ho-kyu Kang ,  Dong-ho Ahn ,  Moon-han Park

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method of forming a shallow trench isolation layer in a semiconductor device is provided, wherein a first trench and a second trench are formed in an area selected from a semiconductor substrate and a sidewall oxide layer, an anti-oxidation liner, and a mask layer are formed on the semiconductor substrate including the inner surfaces of the first and second trenches, in the same order. Using photoresist lithography, the mask layer and the anti-oxidation layer are etched in the second trench. An isolation layer is formed in the first and second trenches by depositing and then chemically and mechanically polishing the dielectric material and the layers underneath until the semiconductor substrate surface is exposed. The first trench provides isolation between N-FETs, an N-FET and a P-FET, an N-FET and other circuit devices, a P-FET and other circuit devices, and other circuit devices and the second trench provides isolation between P-FETs.

公开(公告)号：US07288823B2

公开(公告)日：2007-10-30

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US06645866B2

公开(公告)日：2003-11-11

申请号：US10319534

申请日：2002-12-16

申请人： Tai-su Park ,  Kyung-won Park ,  Jung-woo Park ,  Won-sang Song

发明人： Tai-su Park ,  Kyung-won Park ,  Jung-woo Park ,  Won-sang Song

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/958

摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

摘要翻译： 使用包括氢退火步骤的沟槽隔离方法制造半导体器件的方法，其中在半导体衬底上形成光致抗蚀剂图案，可以在形成光致抗蚀剂图案之前形成衬垫绝缘层，使用光致抗蚀剂蚀刻半导体衬底 图案作为蚀刻掩模以形成沟槽，并且在沟槽中形成隔离层。 为了消除在由隔离层限定的有源区域中产生的损伤，具有隔离层的半导体衬底在氢气氛中退火。

公开(公告)号：US06461937B1

公开(公告)日：2002-10-08

申请号：US09479442

申请日：2000-01-07

申请人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

发明人： Sung-eui Kim ,  Keum-joo Lee ,  In-seak Hwang ,  Young-sun Koh ,  Dong-ho Ahn ,  Moon-han Park ,  Tai-su Park

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.

摘要翻译： 形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。 掩模层可以包括氮化硅。 然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。 接下来，在凹陷抑制层上形成应力消除层。 该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。 然后用沟槽隔离层填充沟槽。 然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。 使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。 凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。 以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。 还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

公开(公告)号：US5985034A

公开(公告)日：1999-11-16

申请号：US925264

申请日：1997-09-08

申请人： Tai-su Park

发明人： Tai-su Park

IPC分类号： H01L21/31 ,  H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  C23C16/00

CPC分类号： H01L21/67115 ,  H01L21/67092 ,  H01L21/76224 ,  H01L21/76877

摘要： There are disclosed an opening filling apparatus and a method for manufacturing a semiconductor device by using the same. An opening of a semiconductor device is filled by using the filling apparatus comprising: a chamber having a rotation shaft, a motor, a plurality of plates arranged in a circular form centering at the rotation shaft, and a heater; and injectors for injecting gas. When the opening of a semiconductor device such as a trench or a contact hole is filled, filling material may move down by using the centrifugal force generated by rotating the substrate, to thereby fill the opening completely without a void.

摘要翻译： 公开了一种开口填充装置及其制造方法。 通过使用填充装置填充半导体装置的开口，所述填充装置包括：具有旋转轴，马达，以所述旋转轴为中心的圆形排列的多个板的加热器; 和注入气体的注射器。 当填充诸如沟槽或接触孔的半导体器件的开口时，填充材料可以通过使用通过旋转衬底产生的离心力向下移动，从而完全填充开口而没有空隙。

公开(公告)号：US5858842A

公开(公告)日：1999-01-12

申请号：US675534

申请日：1996-07-03

申请人： Tai-su Park

发明人： Tai-su Park

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： Methods of forming electrical isolation regions in semiconductor substrates include the steps of forming a first electrical isolation region at a face of a semiconductor substrate, then forming a trench in the semiconductor substrate, laterally adjacent the first electrical isolation region, and then forming a trench isolation region in the trench so that the trench isolation region is contiguous with the first isolation region. In particular, these methods include the steps of forming a pad insulating layer on the face of a semiconductor substrate and then forming a first nitride layer on the pad insulating layer. The first nitride layer is then patterned by removing a portion thereof to define an opening extending opposite an inactive region within the semiconductor substrate. A second nitride layer is then formed on the patterned first nitride layer and in the opening. The second nitride layer is then patterned within the opening by removing a portion thereof extending opposite a portion of the inactive region. The second nitride layer is then used as a mask to selectively form a first isolation region by thermally oxidizing the substrate. The second nitride layer is then removed and followed by the step of etching a laterally adjacent portion of the inactive region to form a trench. The trench is then filled by depositing an oxide layer in the trench and on the first isolation region. Chemical-mechanical polishing is then performed to planarize the deposited oxide layer and the first isolation region and form a single composite isolation region therefrom. Stable isolation characteristics can therefore be obtained because the above sequence of steps reduces the degree of dishing associated with the composite isolation region, even when relatively wide trenches are used for isolation.

摘要翻译： 在半导体衬底中形成电隔离区的方法包括以下步骤：在半导体衬底的表面形成第一电隔离区，然后在半导体衬底中形成沟槽，横向邻近于第一电隔离区，然后形成沟槽隔离 区域，使得沟槽隔离区域与第一隔离区域邻接。 特别地，这些方法包括以下步骤：在半导体衬底的表面上形成衬垫绝缘层，然后在衬垫绝缘层上形成第一氮化物层。 然后通过去除第一氮化物层的一部分来限定与半导体衬底内的非活性区域相对的开口。 然后在图案化的第一氮化物层和开口中形成第二氮化物层。 然后通过除去与非活性区域的一部分相对延伸的部分，在开口内将第二氮化物层图案化。 然后将第二氮化物层用作掩模，以通过热氧化基底来选择性地形成第一隔离区。 然后去除第二氮化物层，随后蚀刻非活性区域的横向相邻部分以形成沟槽的步骤。 然后通过在沟槽和第一隔离区域上沉积氧化物层来填充沟槽。 然后进行化学机械抛光以使沉积的氧化物层和第一隔离区域平坦化，并从其形成单个复合隔离区域。 因此，即使使用较宽的沟槽进行隔离，上述步骤顺序降低了与复合隔离区域相关的凹陷度，因此可以获得稳定的隔离特性。

公开(公告)号：US5824562A

公开(公告)日：1998-10-20

申请号：US506654

申请日：1995-07-25

申请人： Tai-su Park

发明人： Tai-su Park

IPC分类号： H01L21/31 ,  H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/67115 ,  H01L21/67092 ,  H01L21/76224 ,  H01L21/76877

摘要： There are disclosed an opening filling apparatus and a method for manufacturing a semiconductor device by using the same. An opening of a semiconductor device is filled by using the filling apparatus comprising: a chamber having a rotation shaft, a motor, a plurality of plates arranged in a circular form centering at the rotation shaft, and a heater; and means for injecting gas. When the opening of a semiconductor device such as a trench or a contact hole is filled, filling material may move down by using the centrifugal force generated by rotating the substrate, to thereby fill the opening completely without a void.

摘要翻译： 公开了一种开口填充装置及其制造方法。 通过使用填充装置填充半导体装置的开口，所述填充装置包括：具有旋转轴，马达，以所述旋转轴为中心的圆形排列的多个板的加热器; 以及注入气体的装置。 当填充诸如沟槽或接触孔的半导体器件的开口时，填充材料可以通过使用通过旋转衬底产生的离心力向下移动，从而完全填充开口而没有空隙。