公开(公告)号：US20050056888A1

公开(公告)日：2005-03-17

申请号：US10917026

申请日：2004-08-11

申请人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US07288823B2

公开(公告)日：2007-10-30

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Mun Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US07015106B2

公开(公告)日：2006-03-21

申请号：US10917026

申请日：2004-08-11

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/338

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

公开(公告)号：US20060134868A1

公开(公告)日：2006-06-22

申请号：US11316307

申请日：2005-12-21

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

公开(公告)号：US07265011B2

公开(公告)日：2007-09-04

申请号：US10898484

申请日：2004-07-22

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

公开(公告)号：US20050048729A1

公开(公告)日：2005-03-03

申请号：US10898484

申请日：2004-07-22

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

公开(公告)号：US08283714B2

公开(公告)日：2012-10-09

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

公开(公告)号：US07977725B2

公开(公告)日：2011-07-12

申请号：US12171091

申请日：2008-07-10

申请人： Jae-man Yoon ,  Yong-chul Oh ,  Hui-jung Kim ,  Hyun-woo Chung ,  Kang-uk Kim ,  Dong-gun Park ,  Woun-suck Yang

发明人： Jae-man Yoon ,  Yong-chul Oh ,  Hui-jung Kim ,  Hyun-woo Chung ,  Kang-uk Kim ,  Dong-gun Park ,  Woun-suck Yang

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/66666

摘要： An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.

摘要翻译： 集成电路半导体器件包括形成在下基板处并配置有垂直晶体管和平面晶体管中的至少一个的第一晶体管。 在第一晶体管上形成接合绝缘层，并且在接合绝缘层上接合上基板。 在上基板上形成配置有垂直晶体管和平面晶体管中的至少一个的第二晶体管。 第一晶体管和第二晶体管通过互连层连接。

公开(公告)号：US07859064B1

公开(公告)日：2010-12-28

申请号：US11849577

申请日：2007-09-04

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/41

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US20100285645A1

公开(公告)日：2010-11-11

申请号：US12838826

申请日：2010-07-19

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。