公开(公告)号：US08187967B2

公开(公告)日：2012-05-29

申请号：US12458675

申请日：2009-07-20

申请人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

发明人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

IPC分类号： H01L21/4763

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

摘要翻译： 一种制造提供其中限定了单元区域和外围区域的半导体层的非易失性存储器件的方法，其顺序地形成在第一绝缘层，第一导电层，第二绝缘层和第二导电层上 形成用于暴露周边区域的第一导电层的一部分的沟槽，其中通过去除周边区域中的第二导电层和第二绝缘层的部分形成沟槽，进行修整 用于去除所述第二导电层和所述单元区域的所述第二绝缘层的部分的工作，在所述沟槽的侧表面上形成间隔物，以及形成电连接到所述第一导电层的硅化物层，其中所述硅化物层为 通过在间隔物上进行硅化处理而形成。

公开(公告)号：US20140021527A1

公开(公告)日：2014-01-23

申请号：US13719180

申请日：2012-12-18

申请人： Jung-Min Son ,  Woon-kyung Lee

发明人： Jung-Min Son ,  Woon-kyung Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L27/11521

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括电荷存储结构和栅极。 电荷存储结构形成在基板上。 栅极形成在电荷存储结构上。 栅极包括由硅形成的下部和由金属硅化物形成的上部。 栅极的上部具有大于栅极下部的宽度的宽度。

公开(公告)号：US20120238093A1

公开(公告)日：2012-09-20

申请号：US13418585

申请日：2012-03-13

申请人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

发明人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

摘要翻译： 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US20100173485A1

公开(公告)日：2010-07-08

申请号：US12458675

申请日：2009-07-20

申请人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

发明人： Seung-jun Lee ,  Woon-kyung Lee ,  Seung-wan Hong

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile memory device providing a semiconductor layer in which a cell region and a peripheral region are defined, sequentially forming a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer on the cell region and the peripheral region, forming a trench for exposing a portion of the first conductive layer of the peripheral region, wherein the trench is formed by removing portions of the second conductive layer and the second insulating layer in the peripheral region, performing a trimming operation for removing portions of the second conductive layer and the second insulating layer of the cell region, forming a spacer on a side surface of the trench, and forming a silicide layer that is electrically connected to the first conductive layer, wherein the silicide layer is formed by performing a silicidation process on the spacer.

摘要翻译： 一种制造提供其中限定了单元区域和外围区域的半导体层的非易失性存储器件的方法，其顺序地形成在第一绝缘层，第一导电层，第二绝缘层和第二导电层上 形成用于暴露周边区域的第一导电层的一部分的沟槽，其中通过去除周边区域中的第二导电层和第二绝缘层的部分形成沟槽，进行修整 用于去除所述单元区域的所述第二导电层和所述第二绝缘层的部分的工作，在所述沟槽的侧表面上形成间隔物，以及形成电连接到所述第一导电层的硅化物层，其中所述硅化物层为 通过在间隔物上进行硅化处理而形成。

公开(公告)号：US06933195B2

公开(公告)日：2005-08-23

申请号：US09995299

申请日：2001-11-27

申请人： Woon-kyung Lee

发明人： Woon-kyung Lee

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory device includes forming a device isolation layer at a predetermined region of a semiconductor substrate having a cell array region and a peripheral circuit region. The device isolation layer defines a first active region and a second active region in the cell array region and the peripheral circuit region, respectively. A gate conductive layer is formed on the entire surface of the semiconductor substrate having the device isolation layer. The gate conductive layer is patterned to form a floating gate pattern covering the first active region. At this time, the peripheral circuit region is still covered with the gate conductive layer. An inter-gate dielectric layer and a control gate conductive layer are formed on the entire surface of the substrate including the floating gate pattern. The control gate conductive layer and the inter-gate dielectric layer, which are located in the peripheral circuit region, are selectively removed to expose the gate conductive layer in the peripheral circuit region.

摘要翻译： 制造闪存器件的方法包括在具有单元阵列区域和外围电路区域的半导体衬底的预定区域形成器件隔离层。 器件隔离层分别在单元阵列区域和外围电路区域中限定第一有源区和第二有源区。 在具有器件隔离层的半导体衬底的整个表面上形成栅极导电层。 图案化栅极导电层以形成覆盖第一有源区的浮栅图案。 此时，外围电路区域仍然被栅极导电层覆盖。 在包括浮置栅极图案的衬底的整个表面上形成栅极间电介质层和控制栅极导电层。 选择性地去除位于外围电路区域中的控制栅极导电层和栅极间电介质层，以露出外围电路区域中的栅极导电层。

公开(公告)号：US06291308B1

公开(公告)日：2001-09-18

申请号：US09372850

申请日：1999-08-12

申请人： Woon-kyung Lee ,  He-jueng Lee

发明人： Woon-kyung Lee ,  He-jueng Lee

IPC分类号： H01L2176

CPC分类号： H01L27/11293

摘要： A method for fabricating a mask ROM capable of effectively reducing the distance of buried impurity diffusion regions. The method includes stacking a pad oxide layer and a first anti-oxidation layer in sequence in a cell array region and a peripheral circuit region of a semiconductor substrate. The anti-oxidation layer is partially etched to form a first pattern defining an isolation region of the peripheral circuit region and a second pattern defining a buried impurity diffusion region of the cell array region, and a second anti-oxidation layer is stacked, and then the second anti-oxidation layer stacked in the peripheral circuit region is removed, so that the second anti-oxidation layer stacked in the cell array region remains. Then, a field oxide layer is formed in the isolation region of the peripheral circuit region, exposed by the remaining second anti-oxidation layer; and impurities are implanted to form the buried impurity diffusion region.

摘要翻译： 一种制造掩模ROM的方法，其能够有效地减少掩埋的杂质扩散区域的距离。 该方法包括在半导体衬底的单元阵列区域和外围电路区域中依次层叠衬垫氧化物层和第一抗氧化层。 部分蚀刻抗氧化层以形成限定外围电路区域的隔离区域的第一图案和限定电池阵列区域的掩埋杂质扩散区域的第二图案，并且层叠第二抗氧化层，然后 去除在周边电路区域堆叠的第二抗氧化层，从而保留堆叠在电池阵列区域中的第二抗氧化层。 然后，在外围电路区域的隔离区域中形成场氧化物层，由剩余的第二抗氧化层露出; 并且注入杂质以形成掩埋的杂质扩散区域。

公开(公告)号：US5846863A

公开(公告)日：1998-12-08

申请号：US779469

申请日：1997-01-08

申请人： Woon-kyung Lee ,  Sung-bu Jun

发明人： Woon-kyung Lee ,  Sung-bu Jun

IPC分类号： G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/1126 ,  G11C17/123 ,  G11C17/126 ,  H01L27/112

摘要： A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

摘要翻译： 公开了一种半导体存储器件及其制造方法。 该器件包括重复形成的彼此平行延伸的多个有源区，器件隔离区，与有源区和器件隔离区垂直的反复排列的多个第一栅极，由自身形成的源极/漏极区 位于第一栅电极，有源区和器件隔离区中的对准离子注入，以及位于第一栅电极之间的平行于第一栅电极延伸的第二栅极，与第一栅电极共用源极/漏极 ，并使用设备隔离区域作为通道。 因此，能够提高电池积分，能够容易地确保高速运转和良好的收率。

公开(公告)号：US5721698A

公开(公告)日：1998-02-24

申请号：US604785

申请日：1996-02-23

申请人： Woon-kyung Lee ,  Sung-bu Jun

发明人： Woon-kyung Lee ,  Sung-bu Jun

IPC分类号： G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C17/00 ,  H01L29/68

CPC分类号： H01L27/1126 ,  G11C17/123 ,  G11C17/126 ,  H01L27/112

摘要： A semiconductor memory device and a method for manufacturing the same are disclosed. The device includes a plurality of active regions repeatedly formed extending in parallel to each other, a device isolation region, a plurality of first gate electrodes repeatedly arranged being perpendicular to the active region and device isolation region, a source/drain region formed by being self-aligned ion-implanted into the first gate electrode, active region, and device isolation region, and a second gate electrode located between the first gate electrodes, extending in parallel to the first gate electrode, sharing the source/drain with the first gate electrode, and using the device isolation region as a channel. Thus, cell integration can be enhanced, and high speed operation and excellent yields can be easily ensured.

摘要翻译： 公开了一种半导体存储器件及其制造方法。 该器件包括重复形成的彼此平行延伸的多个有源区，器件隔离区，与有源区和器件隔离区垂直的反复排列的多个第一栅极，由自身形成的源极/漏极区 位于第一栅电极，有源区和器件隔离区中的对准离子注入，以及位于第一栅电极之间的平行于第一栅电极延伸的第二栅极，与第一栅电极共用源极/漏极 ，并使用设备隔离区域作为通道。 因此，能够提高电池积分，能够容易地确保高速运转和良好的收率。