公开(公告)号：US20120238093A1

公开(公告)日：2012-09-20

申请号：US13418585

申请日：2012-03-13

申请人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

发明人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

摘要翻译： 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US08906805B2

公开(公告)日：2014-12-09

申请号：US13418585

申请日：2012-03-13

申请人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

发明人： Sang-yong Park ,  Woon-kyung Lee ,  Jin-taek Park

IPC分类号： H01L21/768 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L21/76802 ,  H01L21/311 ,  H01L21/76838 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device includes forming a stacked structure in which 2n (here, n is an integer which is 2 or more) deposited sacrificial layers and 2n deposited insulating layers disposed on the 2n deposited sacrificial layers respectively are alternately deposited in a third direction perpendicular to a first direction and a second direction on a substrate having an upper surface extending in the first and second directions which are perpendicular to each other. Methods include forming a recess group including 2n−1 first recesses penetrating 20 through 2n−1 deposited sacrificial layers and forming a buried insulating layer group including 2n−1 buried insulating layers filling the 2n−1 first recesses respectively. A contact plug group including 2n contact plugs penetrating an uppermost deposited insulating layer of the 2n deposited insulating layers and the 2n−1 buried insulating layers may be formed.

摘要翻译： 一种制造半导体器件的方法包括形成层叠结构，其中分别沉积有牺牲层的2n（n为2以上的整数）和设置在2n个沉积的牺牲层上的2n个沉积的绝缘层交替地沉积在第三 垂直于第一方向和第二方向的方向在具有在彼此垂直的第一和第二方向上延伸的上表面的基板上。 方法包括形成包括通过2n-1个沉积的牺牲层穿透20的2n-1个第一凹部的凹陷组，并且分别形成包括2n-1个第一凹部的2n-1个掩埋绝缘层的掩埋绝缘层组。 可以形成包括穿过2n个沉积绝缘层的最上层的绝缘层和2n-1个绝缘层的2n个接触插塞的接触插塞组。

公开(公告)号：US08653585B2

公开(公告)日：2014-02-18

申请号：US13404047

申请日：2012-02-24

申请人： Eun-sun Youm ,  Sang-yong Park ,  Jin-taek Park ,  Yong-top Kim

发明人： Eun-sun Youm ,  Sang-yong Park ,  Jin-taek Park ,  Yong-top Kim

IPC分类号： H01L29/66

CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/7926

摘要： A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region.

摘要翻译： 一种具有垂直结构的非易失性存储器件及其制造方法，所述非易失性存储器件包括从衬底垂直延伸的沟道区域; 所述栅极电极沿着所述沟道区域的外侧壁设置并且彼此间隔开; 以及沟道垫，其从所述沟道区的一侧延伸到所述沟道区的外部，所述沟道衬垫覆盖所述沟道区的顶表面。

公开(公告)号：US20130252391A1

公开(公告)日：2013-09-26

申请号：US13896819

申请日：2013-05-17

申请人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

发明人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

IPC分类号： H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66477 ,  H01L29/7926

摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.

公开(公告)号：US07816270B2

公开(公告)日：2010-10-19

申请号：US12453307

申请日：2009-05-06

申请人： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

发明人： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

IPC分类号： H01L21/311

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

摘要： A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

摘要翻译： 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

公开(公告)号：US08142986B2

公开(公告)日：2012-03-27

申请号：US12192430

申请日：2008-08-15

申请人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

发明人： Jae-hwang Sim ,  Sang-yong Park ,  Young-ho Lee

IPC分类号： G03F7/20

CPC分类号： H01L27/11573 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11575

摘要： A method of forming fine patterns of a semiconductor device, in which a plurality of conductive lines formed in a cell array region are integrally formed with contact pads for connecting the conductive lines to a peripheral circuit. In this method, a plurality of mold mask patterns, each including a first portion extending in a first direction and a second portion which is integrally formed with the first portion and extends in a second direction, are formed within a cell block on a substrate comprising a film which is to be etched. A first mask layer covering sidewalls and an upper surface of each of the plurality of mold mask patterns is formed on the substrate. First mask patterns are formed by partially removing the first mask layer so that a first area of the first mask layer remains and a second area of the first mask layer is removed. The first area of the first mask layer covers sidewalls of adjacent mold mask patterns from among the plurality of mold mask patterns by being located between the adjacent mold mask patterns, and the second area of the first mask layer covers portions of the sidewalls of the plurality of mold mask patterns, the portions corresponding to an outermost sidewall of a mold mask pattern block.

摘要翻译： 一种形成半导体器件的精细图案的方法，其中形成在单元阵列区域中的多个导线与用于将导线连接到外围电路的接触焊盘一体地形成。 在该方法中，在基板上形成多个模具掩模图案，每个模具掩模图案包括沿第一方向延伸的第一部分和与第一部分整体形成并在第二方向上延伸的第二部分， 要蚀刻的薄膜。 在基板上形成覆盖多个模具掩模图案中的每一个的侧壁和上表面的第一掩模层。 通过部分去除第一掩模层形成第一掩模图案，使得第一掩模层的第一区域保留，并且去除第一掩模层的第二区域。 第一掩模层的第一区域通过位于相邻的模具掩模图案之间而覆盖多个模具掩模图案中的相邻模具掩模图案的侧壁，并且第一掩模层的第二区域覆盖多个模具掩模图案的侧壁的部分 的模具掩模图案，其对应于模具掩模图案块的最外侧壁的部分。

公开(公告)号：US20110034030A1

公开(公告)日：2011-02-10

申请号：US12905318

申请日：2010-10-15

申请人： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jaw-hwang Sim

发明人： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jaw-hwang Sim

IPC分类号： H01L21/302

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

摘要： A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

摘要翻译： 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

公开(公告)号：US10811421B2

公开(公告)日：2020-10-20

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L27/1157 ,  H01L27/11575 ,  H01L23/31 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US20180026041A1

公开(公告)日：2018-01-25

申请号：US15712836

申请日：2017-09-22

申请人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

发明人： Sang-yong Park ,  Kee-jeong Rho ,  Hyeong Park ,  Tae-wan Lim

IPC分类号： H01L27/108 ,  H01L29/792 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/1157 ,  H01L23/31 ,  H01L27/11582

CPC分类号： H01L27/10897 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US08455940B2

公开(公告)日：2013-06-04

申请号：US13100488

申请日：2011-05-04

申请人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

发明人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66477 ,  H01L29/7926

摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.

摘要翻译： 非易失性存储器件包括衬底，从衬底突出的沟道层，围绕沟道层的栅极导电层，设置在沟道层和栅极导电层之间的栅极绝缘层以及与沟道间隔开的第一绝缘层 并设置在栅极导电层的顶部和底部。 栅极绝缘层在栅极导电层和第一绝缘层之间延伸。