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42 条记录 (耗时 0.053 秒)

    Structure and method for hyper-abrupt junction varactors
    11.
    发明授权
    Structure and method for hyper-abrupt junction varactors 有权
    超突变连接变容二极管的结构和方法

    公开(公告)号：US07253073B2

    公开(公告)日：2007-08-07

    申请号：US10707905

    申请日：2004-01-23

    申请人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    发明人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    IPC分类号： H01L21/20 ,  H01L21/8234 ,  H01L21/425

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

    摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

    Structure and method of hyper-abrupt junction varactors
    12.
    发明授权
    Structure and method of hyper-abrupt junction varactors 有权
    超突变结可变电抗器的结构和方法

    公开(公告)号：US07183628B2

    公开(公告)日：2007-02-27

    申请号：US11004877

    申请日：2004-12-07

    申请人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    发明人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    IPC分类号： H01L29/93

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

    摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

    DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH
    15.
    发明申请
    DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH 失效
    深度基础的FAR SUBCOLLECTOR REACHTHROUGH

    公开(公告)号：US20100117189A1

    公开(公告)日：2010-05-13

    申请号：US12691320

    申请日：2010-01-21

    申请人： Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    发明人： Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    IPC分类号： H01L29/06 ,  H01L21/761

    CPC分类号： H01L21/763 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732

    摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

    摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。

    Varied impurity profile region formation for varying breakdown voltage of devices
    20.
    发明授权
    Varied impurity profile region formation for varying breakdown voltage of devices 有权
    用于改变器件击穿电压的不同杂质分布区域形成

    公开(公告)号：US08030167B2

    公开(公告)日：2011-10-04

    申请号：US11839106

    申请日：2007-08-15

    申请人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

    发明人： Douglas D. Coolbaugh ,  Louis D. Lanzerotti ,  Bradley A. Orner ,  Jay S. Rascoe ,  David C. Sheridan ,  Stephen A. St. Onge

    IPC分类号： H01L21/33 ,  H01L27/102 ,  H01L29/73

    CPC分类号： H01L21/8222 ,  H01L21/266 ,  H01L27/0825 ,  H01L29/0821 ,  H01L29/36

    摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.

    摘要翻译： 公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。 在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。 装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。 可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。 还公开了一种半导体器件。