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公开(公告)号：US08105924B2
公开(公告)日：2012-01-31
申请号：US12691320
申请日：2010-01-21
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US07691734B2
公开(公告)日：2010-04-06
申请号：US11680637
申请日：2007-03-01
IPC分类号： H01L21/04
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US20080211064A1
公开(公告)日：2008-09-04
申请号：US11680637
申请日：2007-03-01
IPC分类号： H01L29/06 , H01L21/425
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区可以形成在至少一个深沟槽周围，或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US20100117189A1
公开(公告)日：2010-05-13
申请号：US12691320
申请日：2010-01-21
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L21/763 , H01L29/0821 , H01L29/66272 , H01L29/732
摘要： A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
摘要翻译： 通过将掺杂剂离子注入到初始半导体衬底的区域中，随后半导体材料的外延生长，形成位于超过常规离子注入范围的深度的远的子集电极或掩埋掺杂半导体层。 通过从沉积在邻接远子集电极的至少一个深沟槽中的掺杂材料层向外扩散掺杂剂形成远子集电极的到达区域。 穿通区域可形成为围绕至少一个深沟槽或仅在至少一个深沟槽的一侧上。 如果至少一个沟槽的内部电连接到通孔区域，则可以在至少一个沟槽内的掺杂填充材料上形成金属接触。 如果不是，则在与接触区域接触的次级通过区域上形成金属接触。
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公开(公告)号：US20080087978A1
公开(公告)日：2008-04-17
申请号：US11548310
申请日：2006-10-11
CPC分类号： H01L29/0821 , H01L21/743 , H01L21/8249 , H01L27/0251 , H01L29/66242 , H01L29/737 , H01L29/78
摘要： A structure and method comprises a deep sub-collector located in a first epitaxial layer and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The device further comprises a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 一种结构和方法包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区。 该器件还包括从器件的表面穿过第一和第二外延层到达深子集电极的通孔结构，以及从器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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6.发明授权Design structure with a deep sub-collector, a reach-through structure and trench isolation 有权具有深子集电极的设计结构，通孔结构和沟槽隔离公开(公告)号：US08015538B2
公开(公告)日：2011-09-06
申请号：US11941104
申请日：2007-11-16
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。 该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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公开(公告)号：US20080092094A1
公开(公告)日：2008-04-17
申请号：US11941104
申请日：2007-11-16
IPC分类号： G06F17/50
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译： 本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。 该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。
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公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译： 提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。 所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。 此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。 包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过 所述至少一个半导体通道。 通过采用多个通道，JFET可以提供高导通电流。
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公开(公告)号：US07755161B2
公开(公告)日：2010-07-13
申请号：US12237148
申请日：2008-09-24
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译： 一种器件包括形成在衬底的上部中的第一子集电极和形成在第一外延层的上部中的第一外延层和第二子集电极的下部，以及第二外延层的下部 。 该装置还包括连接第一和第二子集电器的连通结构和形成在第二外延层的一部分中并与第二子集电器和达到通孔结构接触的N阱。 该装置还包括与N阱接触的N +扩散区，与N阱接触的P +扩散区，以及N +和P +扩散区之间的浅沟槽隔离结构。
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公开(公告)号：US07582949B2
公开(公告)日：2009-09-01
申请号：US11870567
申请日：2007-10-11
申请人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
发明人： Xuefeng Liu , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The design structure additionally includes a reach-through structure connecting the first and second sub-collectors, and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. Also, the design structure includes N+ diffusion regions in contact with the N-well, a P+ diffusion region within the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构。 该设计结构包括形成在衬底的上部和第一外延层的下部的第一子集电极和形成在第一外延层的上部中的第二子集电极， 外延层。 该设计结构还包括连接第一和第二子集电器的通孔结构以及形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。 此外，设计结构包括与N阱接触的N +扩散区域，N阱内的P +扩散区域和N +和P +扩散区域之间的浅沟槽隔离结构。
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