公开(公告)号：US08035141B2

公开(公告)日：2011-10-11

申请号：US12607104

申请日：2009-10-28

申请人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

摘要翻译： 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US20100006952A1

公开(公告)日：2010-01-14

申请号：US12169118

申请日：2008-07-08

申请人： Viorel Ontalus ,  Robert Robison

发明人： Viorel Ontalus ,  Robert Robison

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region of and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.

摘要翻译： 一种FET及其制造方法。 该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在栅极电极下方的沟道区域中形成硅区域中的源极和漏极，源极和源极延伸延伸到栅电极下方，漏极延伸延伸到栅电极下方，源极源极 扩展，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。

公开(公告)号：US09041119B2

公开(公告)日：2015-05-26

申请号：US13465159

申请日：2012-05-07

申请人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

发明人： Desmond J. Donegan, Jr. ,  Abhishek Dube ,  Steven Jones ,  Jophy S. Koshy ,  Viorel Ontalus

IPC分类号： H01L29/02 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

摘要翻译： 提供了一种形成具有接近应力的晶体管到晶体管的沟道区域的方法。 该方法包括在衬底的第一区域中形成第一晶体管，在衬底的第一区域的顶部上具有栅极叠层，以及邻近栅堆叠的侧壁的一组间隔物，第一区域包括源极和漏极 第一晶体管的区域; 在所述衬底的第二区域中形成第二晶体管，在所述衬底的所述第二区域的顶部上具有栅极叠层，以及邻近所述栅极叠层的侧壁的一组间隔区，所述第二区域包括所述栅极叠层的源极和漏极区域 第二晶体管; 用光致抗蚀剂掩模覆盖第一晶体管而不覆盖第二晶体管; 在所述第二晶体管的源极和漏极区域中产生凹陷; 并在凹槽中形成应力源。

公开(公告)号：US08741725B2

公开(公告)日：2014-06-03

申请号：US12943084

申请日：2010-11-10

申请人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

发明人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

IPC分类号： H01L29/06

CPC分类号： H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：US08546219B2

公开(公告)日：2013-10-01

申请号：US13272340

申请日：2011-10-13

申请人： Deepal Wehella-Gamage ,  Viorel Ontalus

发明人： Deepal Wehella-Gamage ,  Viorel Ontalus

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7848

摘要： Embodiment of the present invention provides a method of forming transistors such as narrow channel transistors. The method includes creating a transistor region in a substrate; the transistor region being separated from rest of the substrate, by one or more shallow trench isolation (STI) regions formed in the substrate, to include a channel region, a source region, and a drain region; the STI regions having a height higher than the transistor region of the substrate; and the channel region having a gate stack on top thereof; forming spacers at sidewalls of the STI regions above the transistor region; creating recesses in the source region and the drain region with the spacers preserving at least a portion of material of the substrate underneath the spacers along sidewalls of the STI regions; and epitaxially growing source and drain of the transistor in the recesses.

摘要翻译： 本发明的实施例提供了一种形成诸如窄沟道晶体管的晶体管的方法。 该方法包括在衬底中形成晶体管区域; 所述晶体管区域通过在所述衬底中形成的一个或多个浅沟槽隔离（STI）区域与所述衬底的其余部分分离，以包括沟道区域，源极区域和漏极区域; 所述STI区域具有高于所述衬底的晶体管区域的高度; 并且所述沟道区在其顶部具有栅极堆叠; 在晶体管区域上方的STI区域的侧壁处形成间隔物; 在所述源区域和所述漏极区域中产生凹槽，所述间隔物在所述STI区域的侧壁处保留所述衬垫下方的所述衬底的材料的至少一部分; 并且在凹槽中外延生长晶体管的源极和漏极。

公开(公告)号：US08236660B2

公开(公告)日：2012-08-07

申请号：US12764329

申请日：2010-04-21

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：US20120112280A1

公开(公告)日：2012-05-10

申请号：US12943084

申请日：2010-11-10

申请人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

发明人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：US20110260213A1

公开(公告)日：2011-10-27

申请号：US12764329

申请日：2010-04-21

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes at least one monolayer of dopant located within the upper layer of each of the embedded stressor elements. The at least one monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延掺杂的上层 半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的至少一层掺杂剂单层。 所述至少一个掺杂剂单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：US20140035000A1

公开(公告)日：2014-02-06

申请号：US13564862

申请日：2012-08-02

申请人： Viorel Ontalus ,  Pranita Kulkarni ,  Donald R. Wall ,  Zhengmao Zhu

发明人： Viorel Ontalus ,  Pranita Kulkarni ,  Donald R. Wall ,  Zhengmao Zhu

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78687 ,  H01L2029/7858

摘要： Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.

摘要翻译： 碳掺杂半导体材料部分形成在与场效应晶体管的沟道连接的下面的半导体表面的子集上。 碳掺杂半导体材料部分可以通过含碳半导体材料层的选择性外延或通过将碳原子浅入注入下面的半导体表面的表面部分来形成。 碳掺杂的半导体材料部分可以作为层沉积，然后通过蚀刻进行图案化，或者可以在形成一次性掩模间隔物之后形成。 在碳掺杂的半导体材料部分和下面的半导体表面的物理暴露的表面上形成凸起的源区和漏区。 碳掺杂半导体材料部分将掺杂剂扩散部分局部延迟从升高的源极和漏极区域延伸到下面的半导体材料区域中，从而使得能够局部定制掺杂剂分布，以及改变场效应晶体管的器件参数。

公开(公告)号：US08490029B2

公开(公告)日：2013-07-16

申请号：US13421400

申请日：2012-03-15

申请人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

发明人： Anthony G. Domenicucci ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

IPC分类号： G06F17/50

CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。