公开(公告)号：US09640259B2

公开(公告)日：2017-05-02

申请号：US14946796

申请日：2015-11-20

申请人： eMemory Technology Inc.

发明人： Yi-Hung Li ,  Yen-Hsin Lai ,  Ming-Shan Lo ,  Shih-Chan Huang

IPC分类号： H01L27/108 ,  G11C16/10 ,  H01L29/788 ,  G11C16/14 ,  H01L27/02 ,  H01L27/115 ,  G11C16/04 ,  H01L27/11558 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/423 ,  G11C16/24 ,  H01L27/11524 ,  G11C16/34 ,  G11C16/26 ,  H01L29/45

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2216/10 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7882 ,  H01L29/792

摘要： A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

公开(公告)号：US20160079251A1

公开(公告)日：2016-03-17

申请号：US14946796

申请日：2015-11-20

申请人： eMemory Technology Inc.

发明人： Yi-Hung Li ,  Yen-Hsin Lai ,  Ming-Shan Lo ,  Shih-Chan Huang

IPC分类号： H01L27/115 ,  H01L29/45 ,  H01L29/423

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2216/10 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7882 ,  H01L29/792

摘要： A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

摘要翻译： 单多晶硅非易失性存储器（NVM）单元包括半导体衬底上的PMOS选择晶体管和连接到PMOS选择晶体管的PMOS浮栅晶体管串联。 PMOS浮栅晶体管包括在浮置栅极和半导体衬底之间的浮置栅极和栅氧化层。 保护层氧化物层覆盖并与浮动栅极间接接触。 接触蚀刻停止层设置在保护层氧化物层上，使得浮栅与保护层氧化物层与接触蚀刻停止层隔离。

公开(公告)号：US09236453B2

公开(公告)日：2016-01-12

申请号：US14229980

申请日：2014-03-30

申请人： eMemory Technology Inc.

发明人： Yi-Hung Li ,  Yen-Hsin Lai ,  Ming-Shan Lo ,  Shih-Chan Huang

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L29/788 ,  H01L21/336 ,  G11C16/04 ,  H01L29/66 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  H01L29/06 ,  H01L29/423 ,  G11C16/10 ,  G11C16/24

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2216/10 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7882 ,  H01L29/792

摘要： According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

摘要翻译： 根据一个实施例，单多晶硅非易失性存储器（NVM）单元包括半导体衬底上的PMOS选择晶体管和连接到PMOS选择晶体管的PMOS浮栅晶体管串联。 PMOS浮栅晶体管包括在浮置栅极和半导体衬底之间的浮置栅极和栅氧化层。 保护层氧化物层覆盖并与浮动栅极直接接触。 接触蚀刻停止层设置在保护层氧化物层上，使得浮栅与保护层氧化物层与接触蚀刻停止层隔离。