公开(公告)号：US10811597B2

公开(公告)日：2020-10-20

申请号：US16411194

申请日：2019-05-14

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01F41/30 ,  G11C11/16 ,  H01L43/12

Abstract: A magnetoresistive device with a magnetically fixed region having at least two ferromagnetic regions coupled together by an antiferromagnetic coupling region. At least one of the two ferromagnetic regions includes multiple alternating metal layers and magnetic layers and one or more interfacial layers. Wherein, each metal layer includes at least one of platinum, palladium, nickel, or gold, and the interfacial layers include at least one of an oxide, iron, or an alloy including cobalt and iron.

公开(公告)号：US10475986B1

公开(公告)日：2019-11-12

申请号：US15957333

申请日：2018-04-19

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F41/32 ,  H01F10/32

Abstract: A magnetoresistive device includes first and second ferromagnetic regions and an intermediate region formed of a dielectric material between the first and second ferromagnetic regions. A surface of the intermediate region at an interface between the intermediate region and at least one of the first and second ferromagnetic regions may be a plasma treated surface.

公开(公告)号：US09419208B2

公开(公告)日：2016-08-16

申请号：US15046483

申请日：2016-02-18

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

Abstract translation: 磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。 第一电介质的第一表面与自由磁性层的第一表面接触。 磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。 电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料 电极和导体。

公开(公告)号：US09281168B2

公开(公告)日：2016-03-08

申请号：US14298085

申请日：2014-06-06

Applicant: Everspin Technologies, Inc.

Inventor： Chaitanya Mudivarthi ,  Jason Allen Janesky ,  Jijun Sun ,  Frederick Bennett Mancoff ,  Sanjeev Aggarwal

IPC: H01L27/11 ,  H01L27/22 ,  H01J43/12

CPC classification number: H01J43/12 ,  H01L43/12

Abstract: The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs.

Abstract translation: 通过在处理操作期间使磁性碎屑非磁性来改善磁阻器件的磁特性。 通过在存在磁场的情况下退火部分或完全形成的器件来实现进一步的改进，以消除或稳定该器件的磁阻堆叠内的磁微钉扎位置或其他磁异常。 这种磁特性的改善降低了诸如存在于MRAM中的磁阻器件阵列中的开关特性的偏差。

公开(公告)号：USRE50331E1

公开(公告)日：2025-03-04

申请号：US17658470

申请日：2022-04-08

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H10N50/01 ,  G11C11/16 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

公开(公告)号：US12052928B2

公开(公告)日：2024-07-30

申请号：US17397067

申请日：2021-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H10B61/20 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).

公开(公告)号：US11088318B2

公开(公告)日：2021-08-10

申请号：US16376644

申请日：2019-04-05

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: Spin-orbit-torque (SOT) lines are provided near free regions in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT lines injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from a SOT switching line can be used to switching the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional layers or regions may improve the SOT switching efficiency and the thermal stability of magnetoresistive devices including SOT lines.

公开(公告)号：US10910434B2

公开(公告)日：2021-02-02

申请号：US16870099

申请日：2020-05-08

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US10886331B2

公开(公告)日：2021-01-05

申请号：US16380207

申请日：2019-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A method of manufacturing a magnetoresistive device may include forming a first ferromagnetic region, forming an intermediate region on or above the first ferromagnetic region. The intermediate region may be formed of a dielectric material and include nitrogen. The method may also include forming a second ferromagnetic region on or above the intermediate region.

公开(公告)号：US10483320B2

公开(公告)日：2019-11-19

申请号：US16195178

申请日：2018-11-19

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16 ,  G11B5/39

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).