公开(公告)号：US08687418B1

公开(公告)日：2014-04-01

申请号：US12623369

申请日：2009-11-20

Applicant: Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

Inventor： Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Petro Estakhri ,  Parviz Keshtbod

IPC: G11C11/34

CPC classification number: H01F41/303 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/7881

Abstract: An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.

Abstract translation: 本发明的实施例包括非易失性存储单元，其包括以P基底间隔开的第一和第二N-扩散阱。 在第一和第二N-扩散阱和P-基底上形成第一隔离层。 纳米柱电荷陷阱层形成在第一隔离层上，并且包括散布在非导电区域之间的导电纳米柱。 存储单元还包括形成在纳米柱电荷陷阱层上的第二隔离层; 以及形成在第二隔离层上方和纳米柱电荷陷阱层的区域上方的至少一个字线。 纳米柱电荷陷阱层可用于在施加阈值电压时捕获电荷。 随后，可以读取电荷陷阱层以确定存储在非易失性存储单元中的任何电荷，其中电荷陷阱层中存在或不存在电荷对应于位值。

公开(公告)号：US20140050009A1

公开(公告)日：2014-02-20

申请号：US13585774

申请日：2012-08-14

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: G11C11/02 ,  G11C11/21

CPC classification number: G11C11/1673 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

公开(公告)号：US20130267042A1

公开(公告)日：2013-10-10

申请号：US13443818

申请日：2012-04-10

Applicant: Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Yuchen Zhou ,  Jing Zhang ,  Dong Ha Jung ,  Ebrahim Abedifard ,  Rajiv Yadav Ranjan ,  Parviz Keshtbod

IPC: H01L21/02

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.

Abstract translation: 描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。 在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。 电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。 然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。 结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。 本发明的各种实施方案包括增强或优化方法的方法。 如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

公开(公告)号：US08385108B1

公开(公告)日：2013-02-26

申请号：US13429293

申请日：2012-03-23

Applicant: Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Siamack Nemazie ,  Parviz Keshtbod

IPC: G11C11/00

CPC classification number: G11C11/14 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697

Abstract: A method of method of writing to a magnetic memory cell includes selecting a magnetic memory cell of a magnetic memory array to be written to, the magnetic memory cell including a pair of MTJs, and setting a bit line (BL) coupled to the magnetic memory cell to a state that causes current to flow through the pair of MTJs in a manner that causes the direction of current flow through one of the MTJs of the pair of MTJs to be in a direction opposite to that of the other MTJ of the pair of MTJs.

Abstract translation: 写入磁存储单元的方法的方法包括选择要写入的磁存储器阵列的磁存储单元，磁存储单元包括一对MTJ，以及设置耦合到磁存储器的位线（BL） 电池导致电流流过该对MTJ的状态，使得电流流过该对MTJ的MTJ之一的电流的方向处于与该对MTJ的另一个MTJ的方向相反的方向 MTJs。

公开(公告)号：US08313960B1

公开(公告)日：2012-11-20

申请号：US13371380

申请日：2012-02-10

Applicant: Ebrahim Abedifard ,  Parviz Keshtbod

Inventor： Ebrahim Abedifard ,  Parviz Keshtbod

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting.

Abstract translation: 一种制造磁存储元件的方法包括以下步骤：在底部电极的顶部形成永久磁性层，在永久磁性层的顶部形成钉扎层，形成包含阻挡层的磁性隧道结（MTJ） 钉扎层，在MTJ的顶部形成顶部电极，在顶部电极的顶部上形成硬掩模，并且使用硬掩模执行一系列蚀刻工艺以将MTJ和顶部电极的宽度减小到基本上 当检测到钉扎层中的预定材料时，这些蚀刻工艺中的一个停止，从而避免金属沉积到蚀刻工艺的阻挡层上，从而防止短路。

公开(公告)号：US08289757B2

公开(公告)日：2012-10-16

申请号：US12778725

申请日：2010-05-12

Applicant: Parviz Keshtbod ,  Ebrahim Abedifard

Inventor： Parviz Keshtbod ,  Ebrahim Abedifard

IPC: G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/105 ,  H01L27/228

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括嵌入式MRAM和存取晶体管。 嵌入式MRAM形成在多个金属插入层间电介质（ILD）层中，每个层包括分散在其中的金属并形成在存取晶体管的顶部。 在位于靠近位线的ILD层中形成的金属的顶部上形成磁隧道结（MTJ）。 MTJ掩模用于对MTJ进行图案蚀刻，以暴露MTJ。 最终，在位线顶部形成金属并延伸以接触MTJ。

公开(公告)号：US20130244344A1

公开(公告)日：2013-09-19

申请号：US13610587

申请日：2012-09-11

Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Abstract translation: 描述了使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

公开(公告)号：US08488376B2

公开(公告)日：2013-07-16

申请号：US13476879

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。

公开(公告)号：US20130088915A1

公开(公告)日：2013-04-11

申请号：US13475814

申请日：2012-05-18

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: G11C11/14 ,  H01L29/82

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

公开(公告)号：US20130087870A1

公开(公告)日：2013-04-11

申请号：US13476904

申请日：2012-05-21

Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

IPC: H01L29/82

CPC classification number: B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3236 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/303 ,  H01L27/228 ,  H01L43/08

Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.

Abstract translation: 非易失性磁存储元件包括多个层，其中之一是分级的自由层。 分级自由层可以包括各种元素，其中每个元素具有不同的各向异性，或者其可以包括非磁性化合物和磁性区域，其中非磁性化合物形成梯度含量形成独特的形状，例如锥形，菱形或其它形状，并且其厚度 是基于磁性化合物的反应性。