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公开(公告)号：US09859889B2
公开(公告)日：2018-01-02
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo Lee , Young-Su Kwon , Kyung Jin Byun , Jin Ho Han , Nak Woong Eum
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
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12.发明授权Apparatus and method for maintaining cache coherency, and multiprocessor apparatus using the method 有权用于维护高速缓存一致性的装置和方法，以及使用该方法的多处理器装置公开(公告)号：US09372795B2
公开(公告)日：2016-06-21
申请号：US14030543
申请日：2013-09-18
Inventor： Jin Ho Han
IPC: G06F12/08
CPC classification number: G06F12/0815 , G06F12/0831
Abstract: Provided are an apparatus and method for maintaining cache coherency, and a multiprocessor apparatus using the method. The multiprocessor apparatus includes a main memory, a plurality of processors, a plurality of cache memories that are connected to each of the plurality of processors, a memory bus that is connected to the plurality of cache memories and the main memory, and a coherency bus that is connected to the plurality of cache memories to transmit coherency related information between caches. Accordingly, a bandwidth shortage phenomenon may be reduced in an on-chip communication structure, which occurs when using a communication structure between a memory and a cache, and communication for coherency between caches may be simplified.
Abstract translation: 提供了一种用于维持高速缓存一致性的装置和方法，以及使用该方法的多处理器装置。 多处理器装置包括主存储器，多个处理器，连接到多个处理器中的每一个的多个高速缓存存储器，连接到多个高速缓存存储器和主存储器的存储器总线，以及一个一致性总线 其连接到多个高速缓冲存储器以在高速缓存之间传送相关性信息。 因此，在使用存储器和高速缓存之间的通信结构时发生的片上通信结构中可能会减少带宽短缺现象，并且可以简化高速缓存之间的一致性的通信。
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公开(公告)号：US12266400B2
公开(公告)日：2025-04-01
申请号：US17983016
申请日：2022-11-08
Inventor： Min-Hyung Cho , Young-Deuk Jeon , Jin Ho Han
IPC: G11C11/4099 , G11C5/04 , G11C5/06
Abstract: A method for ZQ calibration for a data transmission driving circuit of each memory die in a memory chip package in which memory dies are stacked, includes generating a reference current through a reference resistor connected between a power terminal supplying a power voltage of the data transmission driving circuit and a ground terminal and a first transistor that is diode-connected; supplying first currents corresponding to the reference currents to a pull-up driver of each memory die; performing ZQ calibration of a pull-up driver of a corresponding memory die by comparing a first voltage formed by each first current with a reference voltage formed by the reference current in each of the plurality of memory dies; and performing ZQ calibration of a pull-down driver of the corresponding memory die based on an output impedance of the ZQ calibrated pull-up driver in each of the memory dies.
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公开(公告)号：US12087392B2
公开(公告)日：2024-09-10
申请号：US17565937
申请日：2021-12-30
Inventor： Young-Deuk Jeon , Min-Hyung Cho , Young-Su Kwon , Jin Ho Han
CPC classification number: G11C7/1084 , G11C7/1057 , G11C7/225 , G11C8/18
Abstract: Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
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公开(公告)号：US11341066B2
公开(公告)日：2022-05-24
申请号：US17119387
申请日：2020-12-11
Inventor： Jin Ho Han , Min-Seok Choi , Young-Su Kwon
IPC: G06F13/16 , G06F12/02 , G06F12/1081 , G06F13/28
Abstract: Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
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Patent Agency Ranking
公开(公告)号：US10983878B2
公开(公告)日：2021-04-20
申请号：US16694913
申请日：2019-11-25
Inventor： Jin Ho Han , Young-Su Kwon , Min-Seok Choi
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.
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公开(公告)号：US09824017B2
公开(公告)日：2017-11-21
申请号：US14253349
申请日：2014-04-15
Inventor： Jin Ho Han , Young Su Kwon , Kyoung Seon Shin
IPC: G06F12/00 , G06F12/0875 , G06F12/0831
CPC classification number: G06F12/0875 , G06F12/0831 , G06F12/0833
Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.
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公开(公告)号：US11893392B2
公开(公告)日：2024-02-06
申请号：US17538147
申请日：2021-11-30
Inventor： Ju-Yeob Kim , Jin Ho Han
CPC classification number: G06F9/3885 , G06F9/30036 , G06F9/3887
Abstract: A method for processing floating point operations in a multi-processor system including a plurality of single processor cores is provided. In this method, upon receiving a group setting for performing an operation, the plurality of single processor cores are grouped into at least one group according to the group setting, and a single processor core set as a master in the group loads an instruction for performing the operation from an external memory, and performs parallel operations by utilizing floating point units (FUPs) of all single processor cores in the group according to the instructions.
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公开(公告)号：US11146253B1
公开(公告)日：2021-10-12
申请号：US17105817
申请日：2020-11-27
Inventor： Young-deuk Jeon , Young-Su Kwon , Seong Min Kim , In San Jeon , Min-Hyung Cho , Jin Ho Han
IPC: H03K3/00 , H03K3/3565 , H03K19/0185 , H03K19/00 , H03K5/08 , G11C11/413 , G01R19/165
Abstract: Disclosed is a receiving circuit, which includes a hysteresis detector that receives an input signal corresponding to a first voltage level and outputs a detection signal having a first threshold voltage and a second threshold voltage, and a level shifter that receives the detection signal, converts the first voltage level of the detection signal to a second voltage level higher than the first voltage level so as to be output as an output signal, and outputs a feedback signal of the second voltage level, and the hysteresis detector receives the feedback signal from the level shifter and adjusts the first threshold voltage and the second threshold voltage based on the feedback signal.
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公开(公告)号：US10180904B2
公开(公告)日：2019-01-15
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho Han , Young-Su Kwon , Kyung Jin Byun , Nak Woong Eum
IPC: G06F12/08 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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